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32-bit, 10 ksps, sigma-delta adc with 100 s settling and true rail-to-rail buffers data sheet AD7177-2 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015 analog devices, inc. all rights reserved. technical support www.analog.com features 32-bit data output fast and flexible output rate: 5 sps to 10 ksps channel scan data rate of 10 ksps/channel (100 s settling) performance specifications 19.1 noise free bits at 10 ksps 20.2 noise free bits at 2.5 ksps 24.6 noise free bits at 5 sps inl: 1 ppm of fsr 85 db filter rejection of 50 hz and 60 hz with 50 ms settling user configurable input channels 2 fully differential channels or 4 single-ended channels crosspoint multiplexer on-chip 2.5 v reference (2 ppm/c drift) true rail-to-rail analog and reference input buffers internal or external clock power supply: avdd1 ? avss = 5 v, avdd2 = iovdd = 2.5 v to 5 v split supply with avdd1/avss at 2.5 v adc current: 8.4 ma temperature range: ?40c to +105c 3- or 4-wire serial digital interface (schmitt trigger on sclk) serial port interface (spi), qspi, microwire, and dsp compatible applications process control: plc/dcs modules temperature and pressure measurement medical and scientific multichannel instrumentation chromatography general description the AD7177-2 is a 32-bit low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) - analog-to-digital converter (adc) for low bandwidth inputs. it has a maximum channel scan rate of 10 ksps (100 s) for fully settled data. the output data rates range from 5 sps to 10 ksps. the AD7177-2 integrates key analog and digital signal condition- ing blocks to allow users to configure an individual setup for each analog input channel in use. each feature can be user selected on a per channel basis. integrated true rail-to-rail buffers on the analog inputs and external reference inputs provide easy to drive high impedance inputs. the precision 2.5 v low drift (2 ppm/c) band gap internal reference (with output reference buffer) adds embedded functionality to reduce external component count. the digital filter allows simult aneous 50 hz and 60 hz rejection at a 27.27 sps output data rate. the user can switch between different filter options accord ing to the demands of each channel in the application. the adc automatically switches through each selected channel. further digital processing functions include offset and gain calibration registers, configurable on a per channel basis. the device operates with a 5 v avdd1 supply, or with 2.5 v avdd1/avss, and 2 v to 5 v avdd2 and iovdd supplies. the specified operating temperature range is ?40c to +105c. the AD7177-2 is available in a 24-lead tssop package. functional block diagram avss gpio0 gpio1 xtal1 xtal2/clkio dgnd ref? ref+ refout ain0 ain1 ain2 ain3 ain4 - ? adc 1.8v ldo int ref avdd1 a vdd2 regcap a 1.8v ldo iovdd regcapd gpio and mux i/o control serial interface and control temperature sensor digital filter AD7177-2 buffered precision reference xtal and internal clock oscillator circuitry cs sclk din dout/rdy sync/error crosspoint multiplexer avdd avss rail-to-rail analog input buffers rail-to-rail reference input buffers 12912-001 figure 1.
ad7177- 2 data sheet rev. a | page 2 of 59 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 timing characteristics ................................................................ 7 absolute maximum ratings ............................................................ 9 ther mal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 noise performance and resolution .............................................. 18 getting started ................................................................................ 19 power supplies ............................................................................ 20 digital communication ............................................................. 20 ad7177 - 2 reset .......................................................................... 21 configuration overview ........................................................... 21 circuit description ......................................................................... 26 buffered analog input ............................................................... 26 crosspoint multiplexer .............................................................. 26 ad7177 - 2 reference .................................................................. 27 buffered reference input ........................................................... 28 clock source ............................................................................... 28 digital filters ................................................................................... 29 sinc5 + sinc1 filter ..................................................................... 29 sinc3 filter ................................................................................... 29 single cycle settling ................................................................... 30 enhanced 50 hz and 60 hz rejection filters ......................... 33 operating mode s ............................................................................ 36 continuous conversion mode ................................................. 36 continuous read mode ............................................................. 37 single c onversion mode ........................................................... 38 standby and power - down modes ............................................ 39 calibration ................................................................................... 39 digital interface .............................................................................. 40 checksum p rotection ................................................................. 40 crc calculation ......................................................................... 41 integrated functions ...................................................................... 43 general - purpose i/o ................................................................. 43 external multiplexer control ................................................... 43 delay ............................................................................................ 43 24- bit/32 - bit conversions ......................................................... 43 dout_reset ........................................................................... 43 synchronization .......................................................................... 43 error flags ................................................................................... 44 data_stat ............................................................................... 44 iostrength ........................................................................... 45 internal temperatu re sensor .................................................... 45 grounding and layout .................................................................. 46 register summary .......................................................................... 47 register details ............................................................................... 48 communications register ......................................................... 48 status register ............................................................................. 49 adc mode register ................................................................... 50 interface mode register ............................................................ 51 regi ster check ............................................................................ 52 data register ............................................................................... 52 gpio configuration register ................................................... 53 id register ................................................................................... 54 channel register 0 ..................................................................... 54 channel register 1 to channel regi ster 3 .............................. 55 setup configuration register 0 ................................................ 56 setup configuration register 1 to setup configuration register 3 ..................................................................................... 56 filter configuration register 0 ................................................. 57 filter configuration register 1 to filter configuration register 3 ..................................................................................... 58 offset register 0 ......................................................................... 58 offset register 1 to offset register 3 ....................................... 58 gain register 0 ............................................................................ 58 gain register 1 to gain register 3 ........................................... 58 outline dimensions ....................................................................... 59 ordering guide .......................................................................... 59
data sheet ad7177- 2 rev. a | page 3 of 59 revision history 9 /15 rev . 0 to rev. a change s to figure 12 and figure 13 ............................................. 13 change s to table 37 ........................................................................ 57 change to table 40 and table 42 ................................................... 58 3 /1 5 re vision 0 : initial version
ad7177- 2 data sheet rev. a | page 4 of 59 specifications avdd1 = 4.5 v to 5.5 v, avdd2 = 2 v to 5.5 v, iovdd = 2 v to 5.5 v, avss = dgnd = 0 v, ref+ = 2.5 v, ref? = avss, internal master clock ( mclk ) = 16 mhz, t a = t min to t max (?40c to +105c), unless otherwise noted. table 1 . parame ter test conditions/comments min typ max unit adc speed and performance output data rate (odr) 5 10,000 sps no missing codes 1 32 bits resolution see table 19 to table 23 noise see table 19 to table 23 fir filter rejection see table 23 accuracy integral nonlinearity (inl) all input buffers disabled 1 3.5 ppm of fsr all input buffers enabled 3.5 7.8 ppm of fsr offset error 2 internal short 40 v offset drift internal short 80 nv/c gain error 2 all input buffers disabled 45 100 ppm of fsr all input buffers enabled 2.5 40 ppm of fsr gain drift 0.4 0.75 ppm/c rejection power supply rejection avdd1, avdd2, v in = 1 v 95 db common - mode rejection v in = 0.1 v at dc 95 db at 50 hz, 60 hz 1 20 hz output data rate (post filter), 50 hz 1 hz and 60 hz 1 hz 120 db normal mode rejection 1 50 hz 1 hz and 60 hz 1 hz internal clock, 20 sps odr (postfilter) 71 90 db external clock, 20 sps odr (postfilter) 85 90 db analog inputs differential input range v ref = (ref+) ? (ref?) v ref v absolute voltage limits 1 input buffers disabled avss ? 0.05 avdd1 + 0.05 v input buffers enabled avss avdd1 v analog input current input buffers disabled input current 48 a/v input current drift external clock 0.75 na/v/c internal clock (2.5% clock) 4 na/v/c input buffers enabled input current 30 na input current drift avdd1 ? 0.2 v to avss + 0.2 v 75 pa/c avdd1 to avss 1 na/c crosstalk 1 khz input ?120 db internal reference 100 nf external capacitor to avss output voltage refout, with respect to avss 2.5 v initial accuracy 3 refout, t a = 25c ?0.12 +0.12 % of v temperature coefficient 1 0c to 105c 2 5 ppm/c ? 40c to +105c 3 10 ppm/c reference load current, i load ?10 +10 ma power supply rejection avdd1, avdd2 (line regulation) 90 db load regulation ?v out /?i load 32 ppm/ma
data sheet ad7177- 2 rev. a | page 5 of 59 parame ter test conditions/comments min typ max unit voltage noise e n , 0.1 hz to 10 hz, 2.5 v reference 4.5 v rms voltage noise density e n , 1 khz, 2.5 v reference 215 nv/hz turn - on settling time 100 nf refout capacitor 200 s short - circuit current, i sc 25 ma external reference inputs differential input range v ref = (ref+) ? (ref?) 1 2.5 avdd1 v absolute voltage limits 1 input buffers disabled avss ? 0.05 avdd1 + 0.05 v input buffers enabled avss avdd1 v ref+/ref? input current input buffers disabled input current 72 a/v input current drift external clock 1.2 na/v/c internal clock 6 na/v/c input buffers enabled input current 800 na input current drift 1.25 na/c normal mode rejection 1 see the rejection parameter common - mode rejection 95 db temperature sensor accuracy after user calibration at 25c 2 c sensitivity 470 v/k burnout currents source/sink current analog input buffers must be enabled 10 a general - purpose i/o (gpio0, gpio1 ) with respect to avss input mode leakage current 1 ?10 +10 a floating state output capacitance 5 pf output high voltage, v oh 1 i source = 200 a avss + 4 v output low voltage, v ol 1 i sink = 800 a avss + 0.4 v input high voltage, v ih 1 avss + 3 v input low voltage, v il 1 avss + 0.7 v clock internal clock frequency 16 mhz accuracy ?2.5% +2.5% % duty cycle 50 % output low voltage, v ol 0.4 v output high voltage, v oh 0.8 iovdd v crystal frequency 14 16 16.384 mhz start - up time 10 s external clock (clkio) 16 16.384 mhz duty cycle 1 30 50 70 %
ad7177- 2 data sheet rev. a | page 6 of 59 parame ter test conditions/comments min typ max unit logic inputs input high voltage, v inh 1 2 v iovdd < 2.3 v 0.65 iovdd v 2.3 v iovdd 5.5 v 0.7 iovdd v input low voltage, v inl 1 2 v iovdd < 2.3 v 0.35 iovdd v 2.3 v iovdd 5.5 v 0.7 v hysteresis 1 iovdd 2.7 v 0.08 0.25 v iovdd < 2.7 v 0.04 0.2 v leakage current ?10 +10 a logic output (dout/ rdy ) output high voltage, v oh 1 iovdd 4.5 v, i source = 1 ma 0.8 iovdd v 2.7 v iovdd < 4.5 v, i source = 500 a 0.8 iovdd v iovdd < 2.7 v, i source = 200 a 0.8 iovdd v output low voltage, v ol 1 iovdd 4.5 v, i sink = 2 ma 0.4 v 2.7 v iovdd < 4.5 v, i sink = 1 ma 0.4 v iovdd < 2.7 v, i sink = 400 a 0.4 v leakage current floating state ?10 +10 a output capacitance floating state 10 pf system calibration 1 full - scale (fs) calibration limit 1.05 fs v zero - scale calibration limit ?1.05 fs v input span 0.8 fs 2.1 fs v power requirements power supply voltage avdd1 to avss 4.5 5 5.5 v avdd2 to avss 2 2.5 to 5 5.5 v avss to dgnd ? 2.75 0 v iovdd to dgnd 2 2.5 to 5 5.5 v iovdd to avss for avss < dgnd 6.35 v power supply currents 4 all outputs unloaded, digital inputs connected to iovdd or dgnd full operating mode avdd1 current analog input and reference input buffers disabled, external reference 1.4 1.65 ma analog input and reference input buffers disabled, internal reference 1.75 2 ma analog input and reference input buffers enabled , external reference 13 16 ma each buffer: ain+, ain ? , ref+, ref ? 2.9 ma avdd2 current external reference 4.5 5 ma internal reference 4.75 5.2 ma iovdd current external clock 2.5 2.8 ma internal clock 2.75 3.1 ma external crystal 3 ma standby mode (ldo on) internal reference off, total current consumption 25 a internal reference on, total current consumption 425 a power - down mode full power - down (including ldo and internal reference) 5 10 a
data sheet ad7177- 2 rev. a | page 7 of 59 parame ter test conditions/comments min typ max unit power dissipation 4 full operating mode all buffers disabled, external clock and reference, avdd2 = 2 v, iovdd = 2 v 21 mw all buffers disabled, external clock and reference, all supplies = 5 v 42 mw all buffers disabled, external clock and reference, all supplies = 5.5 v 52 mw all buffers enabled, internal clock and reference, avdd2 = 2 v, iovdd = 2 v 82 mw all buffers enabled, internal clock and reference, all supplies = 5 v 105 mw all buffers enabled, internal clock and reference, all supplies = 5.5 v 136 mw standby mode internal reference off, all supplies = 5 v 125 w internal reference on, all supplies = 5 v 2.2 mw power - down mode full power - down, all supplies = 5 v 25 50 w 1 this s pecification is not production tested but is supported by characterization data at initial product release . 2 following a system or internal zero - scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. a system full - scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 this specification includ es moisture sensitivity level (msl) pre conditioning effects. 4 this specification is with no load on the refout and digital output pins. timing characteristi cs iovdd = 2 v to 5.5 v, dgnd = 0 v, input logic 0 = 0 v, input logic 1 = iovdd, c load = 20 pf, unless otherwise noted. table 2 . parameter limit at t min , t max unit description 1 , 2 sclk t 3 25 ns min sclk high pulse width t 4 25 ns min sclk low pulse width read operation t 1 0 ns min cs falling edge to dout/ rdy active time 15 ns max iovdd = 4.75 v to 5.5 v 40 ns max iovdd = 2 v to 3.6 v t 2 3 0 ns min sclk active edge to data valid delay 4 12.5 ns max iovdd = 4.75 v to 5.5 v 25 ns max iovdd = 2 v to 3.6 v t 5 5 2.5 ns min bus relinquish time after cs inactive edge 20 ns max t 6 0 ns min sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/ rdy high/low write operation t 8 0 ns min cs falling edge to sclk active edge setup time 4 t 9 8 ns min data valid to sclk edge setup time t 10 8 ns min data valid to sclk edge hold time t 11 5 ns min cs rising edge to sclk edge hold time 1 sample tested during initial release to ensure compliance. 2 see figure 2 and figure 3 . 3 th is paramete r is defined as the time required for the output to cross the v ol or v oh limits. 4 the sclk active edge is the falling edge of sclk. 5 dout/ rdy returns high after a read of the data register. in single conversion mode and continuous conversion mode, the same data can b e read again, if required, while dout/ rdy is high, although care must be taken to ensure that subsequent re ads do not occur close to the next output update. if the continuous read feature is enabled, the digital word can be read only once.
AD7177-2 data sheet rev. a | page 8 of 59 timing diagrams t 2 t 3 t 4 t 1 t 6 t 5 t 7 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb 12912-003 figure 2. read cycle timing diagram i = input, o = output cs (i) s clk (i) din (i) msb lsb t 8 t 9 t 10 t 11 12912-004 figure 3. write cycle timing diagram
data sheet ad7177- 2 rev. a | page 9 of 59 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating avdd1, avdd2 to avss ?0.3 v to +6.5 v avdd1 to dgnd ?0.3 v to +6.5 v iovdd to dgnd ?0.3 v to +6.5 v iovdd to avss ?0.3 v to +7.5 v avss to dgnd ?3.25 v to +0.3 v analog input voltage to avss ?0.3 v to avdd1 + 0.3 v reference input voltage to avss ?0.3 v to avdd1 + 0.3 v digital input voltage to dgnd ?0.3 v to iovdd + 0.3 v digital output voltage to dgnd ?0.3 v to iovdd + 0.3 v analog input/digital input current 10 ma operating temperature range ?40c to +105c storage temperature range ?65c to +150c maximum junction temperature 150c lead soldering, reflow temperature 260c esd rating (h uman b ody m odel ) 4 kv stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for a device soldered on a jedec test board for surface - mount packages. table 4 . thermal resistance package type ja unit 24- lead tssop jedec 1 - layer board 149 c/w jedec 2 - layer board 81 c/w esd caution
ad7177- 2 data sheet rev. a | page 10 of 59 pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 9 10 12 11 ref? ref+ refout avdd1 avss regcapa ain4 avdd2 xtal1 din dout/rdy xtal2/clkio 20 21 22 23 24 19 18 17 16 15 14 13 ain2 ain1 ain0 regcapd gpio0 gpio1 dgnd iovdd sclk cs sync/error ain3 AD7177-2 top view (not to scale) 12912-002 figure 4 . pin configuration table 5 . pin function descriptions 1 pin no. mnemonic type 2 description 1 ain4 ai analog input 4. this pin is electable through the crosspoint multiplexer. 2 ref? ai reference input negative terminal. ref? can span from avss to avdd1 ? 1 v . 3 ref+ ai reference input positive terminal. an external reference can be applied between ref+ and ref?. ref+ can span from avss + 1 v to avdd1 . t he device functions with a reference magnitude from 1 v to avdd1. 4 refout ao buffered output of internal reference. the output is 2.5 v with respect to avss. 5 regcapa ao analog low dropout ( ldo ) regulator output. decouple this pin to avss using a 1 f and a 0.1 f capacitor. 6 avss p negative analog supply. this supply ranges from ?2.75 v to 0 v and is nominally set to 0 v. 7 avdd1 p analog supply voltage 1. this voltage is 5 v 10% with respect to avss. avdd1 ? avss can be a single 5 v supply or a 2.5 v split supply. 8 avdd2 p ana log supply voltage 2. this voltage ranges from 2 v to 5 v with respect to avss. 9 xtal1 ai input 1 for crystal. 10 xtal2/clkio ai/di input 2 for crystal/ clock input or output . the functionality of this pin is b ased on the clockse l b its in the adcmode r egister . there are four options available for selecting the mclk source : internal oscillator : no output. internal oscillator : output to xtal2/clkio . operates at iovdd logic level. external clock : input to xtal2/clkio . input must be at iovdd logic level. external crystal : connected between xtal1 and xtal2/clkio . 11 dout/ rdy do serial data output/data ready output. dout/ rdy i s a dual purpose pin . it functions as a serial data output pin to access the output shift register of the adc. the output shift register can contain data from any of the on - chip data or control registers. the data - word/control word information is placed on the dout/ rdy pin on the sclk falling edge and i s valid on the sclk rising edge. when cs is high, the dout/ rdy output is t hree - stated . when cs is low, dout/ rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge can be used as an interrupt to a processor, indicating that valid data is available. 12 din di serial da ta input to the input shift register on the adc. data in this shift register is transferred to the control registers in the adc, with the register address (ra) bits of the communications register identifying the appropriate register. data is clocked in on the rising edge of sclk. 13 sclk di serial clock input. this serial clock input is for data transfers to and from the adc. the sclk pin has a schmitt triggered input, making the interface suitable for opto - isolated applications. 14 cs di chip select input. this pin is an active low logic input used to select the adc. cs c an be used to select the adc in systems with more than one device on the serial bus. cs can be hardwired low, allowing the adc to op erate in 3 - wire mode with sclk, din, and dout used to interface with the device. when cs is high, the dout/ rdy output is three - stated .
data sheet ad7177- 2 rev. a | page 11 of 59 pin no. mnemonic type 2 description 15 sync / error di/o synchronization input/error input or output. this pin can be switched between a logic input and a logic output in the gpiocon register. when the synchronization input ( sync ) is enabled, this pin allows synchronization of the digital filters and analog modulators whe n using multiple ad7177 - 2 devices . for more information , see the synchronization section . when the synchronization input is disabled, this pin can be used in one of three modes: active low error input mode: this mode sets the adc_error bit in the status register. active low, open - drain error output mode: the status register error bits are mapped to the error output . the sync / error pins of multiple devices can be wired together to a common pull - up resistor so that an error on any device can be observed. general - purpose output mode: the status of the pin is controlled by the err_dat bit in the gpiocon register. the pin is referen ced between iovdd and dgnd, as opposed to the avdd1 and avss levels used by the gpio x pins. the pin has an active pull -up circuit in this case. 16 iovdd p digital i/o supply voltage. the iovdd voltage ranges from 2 v to 5.5 v . iovdd is independent of avdd2. for example, iovdd can be operated at 3 v when avdd2 equals 5 v, or vic e versa. if avss is set to ?2.5 v, the voltage on iovdd must not exceed 3.6 v. 17 dgnd p digital ground. 18 regcapd ao digital ldo regulator output. this pin is for decoupling purposes only. decouple this pin to dgnd using a 1 f and a 0.1 f capacitor. 19 gpio0 di/o general - purpose input/output 0 . the pin is referenced between avdd1 and avss levels. 20 gpio1 di/o general - purpose input/output 1 . the pin is referenced between avdd1 and avss levels. 21 ain0 ai analog input 0. this pin is s electable through the crosspoint multiplexer. 22 ain1 ai analog input 1. this pin is s electable through the crosspoint multiplexer. 23 ain2 ai analog input 2. this pin is selectable through the crosspoint multiplexer. 24 ain3 ai analog input 3. this pin is selectable through the crosspoint multiplexer. 1 note that, throughout this data sheet, the dual function pin names are referenced by the relevant function only. 2 ai is analog input, ao is analog o utput , p is power s upply , di is digital input, do is digital output, and di/o is bidirectional digital input/output .
ad7177- 2 data sheet rev. a | page 12 of 59 typical performance characteristics avdd1 = 5 v, avdd2 = 5 v , iovdd = 3.3 v, t a = 25 c , unless otherwise noted. 2147453700 2147453750 2147453800 2147453850 2147453900 2147453950 2147454000 0 33 66 99 132 165 198 231 264 297 330 363 396 429 462 495 528 561 594 627 660 693 726 759 792 825 858 891 924 957 990 adc code sample number 12912-005 figure 5. noise (analog input buffers disabled, v ref = 5 v, output data rate = 5 sps , 32 - bit data output) sample number 2147447000 2147448000 2147449000 2147450000 2147451000 2147452000 2147453000 2147454000 2147455000 2147456000 2147457000 2147458000 0 33 66 99 132 165 198 231 264 297 330 363 396 429 462 495 528 561 594 627 660 693 726 759 792 825 858 891 924 957 990 adc code 12912-006 figure 6. noise (analog input buffers disabled, v ref = 5 v, output data rate = 10 ksps , 32 - bit data outpu t) sample number 0 33 66 99 132 165 198 231 264 297 330 363 396 429 462 495 528 561 594 627 660 693 726 759 792 825 858 891 924 957 990 adc code 2147455850 2147455900 2147455950 2147456000 2147456050 2147456100 2147456150 2147456200 2147456250 12912-007 figure 7 . noise (analog input buffers enabled, v ref = 5 v, output data rate = 5 sps) 2147453791 2147453799 2147453807 2147453815 2147453823 2147453831 2147453839 2147453847 2147453855 2147453863 2147453871 2147453879 2147453887 2147453895 2147453903 21474539 1 1 2147453919 2147453927 2147453935 2147453943 2147453951 0 20 40 60 80 100 120 140 160 sample count adc code 12912-008 figure 8. histogram (analog input buffers disabled, v ref = 5 v, output data rate = 5 sps , 32 - bit data output ) 2147450526 2147450830 214745 1 134 2147451438 2147451742 2147452046 2147452350 2147452654 2147452958 2147453262 2147453566 2147453870 2147454174 2147454478 2147454782 2147455086 2147455390 2147455694 2147455998 2147456302 2147456606 adc code 0 20 40 60 80 100 120 140 sample count 12912-009 figure 9. histogram (analog input buffers disabled, v ref = 5 v, output data rate = 10 ksps , 32 - bit data output ) 2147455974 2147455985 2147455996 2147456029 2147456018 2147456007 2147456040 2147456051 2147456062 2147456073 2147456084 2147456095 2147456106 2147456 1 17 2147456128 2147456139 2147456150 2147456161 2147456172 2147456183 2147456194 adc code 0 20 40 60 80 100 120 140 160 sample count 12912-010 figure 10 . histogram (analog input buffers enabled, v ref = 5 v, output data rate = 5 sps)
data sheet ad7177- 2 rev. a | page 13 of 5 9 0 33 66 99 132 165 198 231 264 297 330 363 396 429 462 495 528 561 594 627 660 693 726 759 792 825 858 891 924 957 990 2147448000 2147450000 2147452000 2147454000 2147456000 2147458000 2147460000 2147462000 adc code sample number 12912-0 1 1 figure 11 . noise (analog input buffers enabled, v ref = 5 v, output data rate = 10 ksps) 0 1 2 3 4 5 6 8 10 7 9 0 1 2 3 4 5 noise (v rms) input common-mode voltage (v) 12912-301 analog input buffers on analog input buffers off figure 12 . noise vs. input common - mode voltage, analog input buffers on and off 0 1 2 3 4 5 6 8 10 7 9 0 16 14 12 10 8 6 4 2 noise (v rms) frequency (mhz) 12912-302 analog input buffers on analog input buffers off figure 13 . noise vs. external master clock frequency, analog input buffers on and off 2147452393 2147452810 2147453227 2147454478 2147454061 2147453644 2147454895 2147455321 2147455729 2147456146 2147456563 2147456980 2147457397 2147457814 2147458231 2147458648 2147459065 2147459482 2147459899 2147460316 2147460733 adc code 0 20 40 60 80 100 120 140 160 sample count 12912-014 figure 14 . histogram (analog input buffers enabled, v ref = 5 v, output data rate = 10 ksps) 1 10k 1k 100 10 output code sample number 16660000 16680000 16700000 16720000 16740000 16760000 16780000 16800000 continuous conversion?reference disabled standby?reference disabled standby?reference enabled 12912-225 figure 15 . internal reference settling time 1 1m 100k 10k 1k 100 10 cmrr (db) v in frequency (hz) ?120 ?100 ?80 ?60 ?40 ?20 0 12912-226 figure 16 . common - mode rejection ratio (cmrr) vs. v in frequency (v in = 0.1 v)
ad7177- 2 data sheet rev. a | page 14 of 59 10 70 60 50 40 30 20 cmrr (db) v in frequency (hz) ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 12912-227 figure 17 . common - mode rejection ratio (cmrr) vs. v in frequency (v in = 0.1 v, 10 hz to 70 hz, output data rate = 20 sps , enhanced filter) 1 10 100 1k 10k 100k 1m 10m 100m psrr (db) v in frequency (hz) ?130 ?120 ?110 ?100 ?90 ?60 ?70 ?80 avdd1?external 2.5v reference avdd1?internal 2.5v reference 12912-228 figure 18 . power supply rejection ratio (psrr) vs. v in frequency ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 inl (ppm of fsr) v in (v) ?20 ?15 ?10 ?5 0 5 10 15 20 internal 2.5v ref, analog input buffers off internal 2.5v ref, analog input buffers on external 2.5v ref, analog input buffers off external 2.5v ref, analog input buffers on external 5v ref, analog input buffers off external 5v ref, analog input buffers on 12912-229 figure 19 . integral nonlinearity (inl) vs. v in (differential input) sample count inl error (ppm) 0 5 10 15 30 25 20 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 12912-230 figure 20 . integral nonlinearity (inl) distribution histogram (differential input, a ll input buffers enabled, v ref = 2.5 v external , 100 u nits ) sample count inl error (ppm) 0 5 10 15 30 25 20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 12912-231 figure 21 . integral nonlinearity (inl) distribution histogram (differential input, a ll input buffers disabled, v ref = 2.5 v external , 100 u nits ) sample count inl error (ppm) 0 5 10 15 30 25 20 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 12912-232 figure 22 . integral nonlinearity (inl) distribution histogram (a ll input buffers enabled, differential input, v ref = 5 v external , 100 u nits )
data sheet ad7177- 2 rev. a | page 15 of 59 sample count inl error (ppm) 0 5 10 15 30 25 20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 12912-233 figure 23 . integral nonlinearity (inl) distribution histogram (a ll input buffers disabled, differential input, v ref = 5 v external , 100 u nits ) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?40 ?20 0 20 40 60 80 100 inl (ppm of fsr) temperature (c) buffer disabled buffer enabled 12912-234 figu re 24 . integral nonlinearity (inl) vs. temperature (differential input, v ref = 2.5 v external) sample count frequency (mhz) 0 5 10 15 50 45 40 35 30 25 20 15.98 15.99 16.00 16.01 16.02 16.03 16.04 16.05 12912-235 figure 25 . internal oscillator frequency/accuracy distribution histogram (100 u nits) ?40 ?20 0 20 40 60 80 100 frequency (hz) temperature (c) 15600000 15700000 15800000 15900000 16000000 16100000 16200000 16300000 16400000 12912-236 figure 26 . internal oscillator frequency vs. temperature ?40 ?20 0 20 40 60 80 100 error (v) temperature (c) ?0.0010 ?0.0005 0 0.0010 0.0005 12912-237 figure 27 . absolute reference error vs. temperature sample count offset error (v) 0 5 10 15 50 45 40 35 30 25 20 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 12912-238 figure 28 . offset error distribution histogram (internal short , 248 u nits)
ad7177- 2 data sheet rev. a | page 16 of 59 sample count offset drift error (nv/c) 0 5 10 15 35 30 25 20 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 12912-239 figure 29 . offset error drift distribution histogram (internal short , 248 u nits) sample count gain error (ppm/fsr) 0 5 10 15 40 35 30 25 20 ?4 ?3 ?2 ?1 0 1 2 3 4 12912-240 figure 30 . gain error distribution histogram (a ll input buffers enabled , 100 u nits) sample count gain error (ppm/fsr) 0 5 10 15 30 25 20 34 35 36 37 38 39 40 41 42 43 12912-241 figure 31 . gain error distribution histogram (a ll input buffers disabled , 100 u nits ) sample count gain error drift (ppm/fsr) 0 5 10 15 25 20 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 12912-242 figure 32 . gain error drift distribution histogram (a ll input buffers enabled , 100 u nits) sample count gain error drift (ppm/fsr) 0 5 10 15 40 35 30 25 20 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 12912-243 figure 33 . gain err or drift distribution histogram (a ll input buffers disabled , 100 u nits ) ?40 ?20 0 20 40 60 80 100 supply current (a) temperature (c) 0 0.025 0.020 0.015 0.010 0.005 buffers disabled buffers enabled 12912-244 figure 34 . supply current vs. temperature (continuous conversion mode)
data sheet ad7177- 2 rev. a | page 17 of 59 ?40 ?20 0 20 40 60 80 100 supply current (a) temperature (c) 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 12912-245 figure 35 . supply current vs. temperature (power - down mode) sample count temperature delta (c) 0 2 4 6 18 14 16 12 10 8 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 12912-246 figure 36 . temperatur e sensor distribution histogram (uncalibrated , 100 u nits ) sample count current (a) 0 5 10 15 35 30 25 20 9.60 9.65 9.70 9.75 9.80 9.85 9.90 9.95 10.00 10.05 10.10 12912-247 figure 37 . burnout current distribution histogram (100 u nits) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 analog input current (na) input voltage (v) ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 ?40c, ain+ ?40c, ain? +25c, ain+ +25c, ain? +105c, ain+ +105c, ain? 12912-248 figure 38 . analog input current vs. input voltage (v cm = 2.5 v , all input buffers enabled ) ?40 ?20 0 20 40 60 80 100 analog input current (na) temperature (c) ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 ain+ = avdd1 ? 0.2v ain? = avss + 0.2v ain+ = avdd1 ain? = avss 12912-249 figure 39 . analog input current vs. temperature (all input buffers enabled)
ad7177- 2 data sheet rev. a | page 18 of 59 noise performance an d resolution table 6 and table 7 show the rms noise, peak - to - peak noise, effective resolution , and the noi se free (peak - to - peak) resolution of the ad7177 - 2 for various output data rates a nd filters. the numbers given are for the bipolar input range with an external 5 v reference. these numbers are typical and are generated with a differential input voltage of 0 v when the adc is continuously converting on a single channel. it is important to note that the peak - to - peak resolution is calculated based on the peak - to - peak noise. the peak - to - peak resolution represents the resolution for which there is no code flicker. table 6 . rms noise and peak -to - peak resolution vs. output data rate using a sinc5 + sinc1 filter (default) 1 output data rate (sps) rms noise (v rms) effective resolution (bits) peak - to - peak noise (v p - p) peak - to - peak resolution (bits) input buffers disabled 10,000 2.5 21.9 18.3 19.1 1000 0.77 23.6 5.2 20.9 59.92 0.19 25.8 1.1 23.1 49.96 0.18 26 0.95 23.3 16.66 0.1 26.7 0.45 24.1 5 0.07 27.3 0.34 24.6 input buffers enabled 10,000 3 21.7 23 18.7 1000 0.92 23.4 5.7 20.7 59.98 0.23 25.7 1.2 23.0 49.96 0.2 26 1 23.3 16.66 0.13 26.6 0.66 23.9 5 0.07 26.7 0.32 24.6 1 selected rates only, 1000 samples. table 7 . rms noise and peak -to - peak resolution vs. output data rate using a sinc3 filter 1 output data rate (sps) rms noise (v rms) effective resolution (bits) peak - to - peak noise (v p - p) peak - to - peak resolution (bits) input buffers disabled 10,000 1.8 22.4 14 19.4 1000 0.56 24 3.9 21.3 60 0.13 26.3 0.8 23.6 50 0.13 26.5 0.7 23.8 16.66 0.07 27 0.37 24.3 5 0.05 27.5 0.21 24.8 input buffers enabled 10,000 2.1 22.2 16 19.3 1000 0.71 23.7 4.5 21.1 60 0.17 25.8 1.1 23.1 50 0.15 26.2 0.83 23.5 16.66 0.12 26.8 0.6 24.1 5 0.08 27.2 0.35 24.5 5 0.08 24 0.35 24 1 selected rates only, 1000 samples.
data sheet ad7177- 2 rev. a | page 19 of 59 getting started the ad7177 - 2 offers the user a fast settling, high resolution, multiplexed adc with high levels of configurability. the ad7177 - 2 includes the following features: ? two fully differential or four single - end ed analog inputs. ? a c rosspoint multiplexer selects any analog input combina - tion as the input signals to be converted, routing them to the modulator positive or negative input. ? true rail - to - rail buffered analog and reference inputs. ? fully differential inpu t or single - ended input relative to any analog input. ? per channel configurability up to four different setups can be defined. a separate setup can be mapped to each of the channels. each set up allows the user to configure whether the b uffers are e nabled or d isabled , g ain and offset correction , f ilter type , o utput data rate , and r eference source selection (internal/external) . the ad7177 - 2 includes a precision 2.5 v low drift ( 2 ppm/c) band gap internal reference. this reference can be used for the adc conversions, reducing the external component count. alternatively, the reference can be output to the refout pin to be used as a low noise biasing voltage for external circuitry. an example of this is using the refout signal to set the in put common mode for an external amplifier. the ad7177 - 2 includes two separate linear regulator blocks for both the analog and digital circuitry. the analog ldo regulates the avdd2 supply to 1.8 v , supplying the adc core. the user can tie the avdd1 and avdd2 supplies together for an eas y connection. if there is already a clean analog supply rail in the system in the range of 2 v (min imum ) to 5 .5 v (max imum ) , the user can also choose to connect this to the avdd2 input, allowing lower power dissipation. dgnd AD7177-2 iovdd cs sync/error sync/error regcapd refout avss 0.1f regcapa avdd2 avdd1 xtal1 gpio1 4 2 3 1 24 23 22 21 19 20 9 10 11 12 13 14 15 16 17 18 7 8 5 6 6 8 5 3 1 4 7 2 ref? ref+ 2.5v reference output 4.7f 0.1f 0.1f v out gnd nc v in 0.1f 4.7f v in 0.1f adr445 iovdd avdd2 0.1f avdd1 0.1f cx1 16mhz cx2 0.1f 1f 0.1f 1f general-purpose i/o 0 and general-purpose i/o 1 output high = avddx output low = avss optional external crystal circuitry capacitors gpio0 clkin optional external clock input ain0 ain1 ain2 ain3 ain4 gpio0 gpio1 xtal2/clkio dout/rdy din sclk cs dout/rdy din sclk 0.1f 12912-051 tp nc tp trim figure 40 . typical connection diagram
ad7177- 2 data sheet rev. a | page 20 of 59 the linear regulator for the digital iovdd supply per forms a similar function, regulating the input voltage applied at the iovdd pin to 1.8 v for the internal digital filtering. the serial interface signals always operate from the iovdd supply seen at the pin. this means that if 3.3 v is applied to the iovdd pin, the interface logic inputs and outputs operate at this level. the ad7177 - 2 can be used across a wide variety of applications, providing high resolution and accuracy. a sample of these scenarios is as follows: ? fast scanning of analog input channels using the in ternal multiplexer ? fast scanning of analog input channels using an exte rnal multiplexer with automatic control from the gpios. ? high resolution at lower speeds in either channel scanning or adc per channel applications ? single adc per channel . t he fast low latency output allows further application specific filtering in an exter nal micro - controller, dsp, or fpga power supplies the ad7177 - 2 has three independ ent power suppl ies : avdd1, avdd2, and iovdd. avdd1 powers the crosspoint multiplexer and integrated analog a nd reference input buffers . avdd1 is referenced to avss , and av dd1 ? avss = 5 v only. av dd1 ? avs s can be a single 5 v supply or a 2.5 v split su pply. the split supply operation allows true bipolar inputs. when using split supplies, consider the absolute maximum ratings (see the absolute maximum ratings section) . avdd2 powers the internal 1.8 v analog ldo regulator. this regulator powers the adc core. avdd2 is referenced to avss, and av dd2 ? avss can range from to 2 v (min imum ) to 5.5 v (max imum). iovdd powers the internal 1.8 v digital ldo regulator. this regulator powers the digital logic of the adc. iovdd sets the voltage levels for the spi interface of the adc. iovdd is refer - enced to dgnd, and iovdd ? dgnd can vary from 2 v (minimum) to 5.5 v (max imum ) . digital communicatio n the ad7177 - 2 has a 3 - or 4 - wire spi interf ace that is compatible with qspi?, microwire?, and dsps. the interface operates in spi mode 3 and can be operated with cs tied low. in spi mode 3, sclk idles high, the falling edge of sclk is the drive edge, and the rising edge of sclk is the sample edge. this means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. drive edge sample edge 12912-052 figure 41 . spi mode 3 sclk edges accessing the adc register map the communications register controls access to the full register map of the adc. this register is an 8 - bit write only register. on power - up or after a reset, the digital interface default s to a state where it is expect ing a write to the communications register; therefore, all communi cation begins by writing to the communications register. the data written to the communications register determines which register is being accessed and if the next operation is a read or write. the register address bits (ra[5:0]) determine the specific re gister to which the read or write operation applies. when the read or write operation to the selected register is complete, the i nterface returns to its default state, where it expects a write operation to the communications register. figure 42 and figure 43 illustrate writing to and reading from a register by first writing the 8 - bit command to the communications register , followed by the data for that register. din sclk cs 8-bit command 8 bits, 16 bits, or 24 bits of data cmd data 12912-053 figure 42 . writing to a register (8- bit command with register address followed by data of 8 bits , 16 bits , or 24 bits; data length on din is dependent on the register selected) din sclk cs 8-bit command 8 bits, 16 bits, 24 bits, or 32 bits output cmd dat a dout/rd y 12912-054 figure 43 . reading from a register (8- bit command with register address followed by data of 8 bits , 16 bits , or 24 bits; data length on dout is dependent on the register selected) reading the id register is the recommended method for verifying correct communication w ith the device. the id register is a read only register and contains the value 0x4fdx for the ad7177 - 2 . the communications register and the id register details are described in table 8 and table 9 , respectively .
data sheet ad7177- 2 rev. a | page 21 of 59 ad7177 - 2 reset in situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with din high returns the adc to its default state by resetting the entire device , including the register contents. alternatively, if cs is being used with the digital interface, returning cs high sets the digital interface to its default state and halts any serial interface operation. configuration overvi ew after power - on or reset, the ad7177 - 2 default configuration s are as follows. note that only a few of the register setting options are shown; this list is just an example. for full register information, see the reg ister details section. ? channel configuration. ch0 is enabled, ain0 is selected as the positive input, and ain1 is selected as the negative input. setup 0 is selected. ? setup configuration. th e internal reference and t he analog input buffers are enabled. the reference input buffers are disabled. ? filter configuration. the s inc5 + sinc 1 filter is selected and the maximum output data rate of 10 ksps is selected. ? adc mode. continuous conversion mode and the internal oscillator are enabled. ? interface mode. crc and the data + status output are disabled. figure 44 shows an overview of the sugges ted flow for changing the adc configuration, divided into the following three blocks: ? channel configuration (see box a in figure 44) ? setup configuration (see box b in figure 44) ? adc mode and interface mode configurati on (see box c in figure 44) channel configuration the ad7177 - 2 has four independent channels and four independ - ent s etups. the user can select any of the analog input pairs on any chan nel, as well as any of the four setups for any channel, giving the user full flexibility in the channel configuration. this also allows per channel configuration when using differential inputs and single - ended inputs because each channel can have its own d edicated setup. channel registers the channel registers are used to select which of the five analog input pins (ain0 to ain4) are used as either the positive analog input (ain+) or the negative analog input (ain?) for that channel. this register also conta ins a channel enable/disable bit and the setup selection bits, which are used to select from the four available setups for this channel. when the ad7177 - 2 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from channel 0 to channel 3. if a channel is disabled , it is skipped by the sequencer. details of the channel register for channel 0 are shown in table 10. adc mode and interface mode configuration select adc operating mode, clock source, enable crc, data + status, and more setup configuration 4 possible adc setups select filter order, output data rate, and more channel configuration select positive and negative input for each adc channel select one of 4 setups for adc channel a b c 12912-044 figure 44 . suggested adc configuration flow table 8 . communications register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] wen r/ w ra 0x00 w table 9 . id register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x07 id [15:8] id[15:8] 0x4fdx r [7:0] id[7:0] table 10 . channel 0 register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x10 ch0 [15:8] ch_en0 r eserved setup_sel[2:0] reserved ainpos0[4:3] 0x8001 rw [7:0] ainpos0[2:0] ainneg0
ad7177- 2 data sheet rev. a | page 22 of 59 adc setups the ad7177 - 2 has four independent setups . each setup consists of the following four registers: ? setup configuration register ? filter configuration register ? gain register ? offset register for example, setup 0 consists of setup configuration register 0, filter configuration register 0, gain register 0 , and offset register 0 . figure 45 shows the grouping of these registers . the setup is selectable from the channel registers (see the channel configuration section ), which allows each channel to be assigned to one of four separate setups. table 11 through table 14 show the four registers associated with setup 0. this structure is repeated for setup 1 to setup 3. setup configuration registers the setup configuration registers allow the user to select t he output coding of the adc by selecting between bipolar and unipolar. in bipolar mode, the adc accepts negative differential input voltages, and the output coding is offset binary. in unipolar mode, the adc accepts only positive differential voltages, and the coding is straight binary. in either case, the input voltage must be within the avdd1/ avss supply voltages. the user can select the reference source using th e s e register s . three options are available: an internal 2.5 v reference, an external referenc e connected between the ref+ and ref? pins , or av dd 1 ? avss. the analog input and reference input buffers can also be enabled or disabled using this register. filter configuration registers the filter configuration register s select which digital filter is used at the output of the adc modulator. the order of the filter and the output data rate is selected by setting the bits in this register. for more information, see the digital filters section. setup config registers filter config registers offset registers gain registers* select peripheral functions for adc channel select digital filter type and output data rate data output coding reference source input buffers sinc5 + sinc1 sinc3 sinc3 map enhanced 50hz and 60hz gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x28 0x29 0x2a 0x2b 0x38 0x39 0x3a 0x3b 0x30 0x31 0x32 0x33 setupcon3 setupcon0 setupcon2 setupcon1 filtcon3 filtcon0 filtcon2 filtcon1 gain3 gain0 gain2 gain1 offset3 offset0 offset2 offset1 12912-045 figure 45 . adc setup register grouping table 11 . setup configuration 0 register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x20 setupcon0 [15:8] reserved bi_unipolar0 refbuf0+ refbuf0? ainbuf0+ ainbuf0? 0x1320 rw [7:0] burnout_en0 reserved ref_sel0 reserved table 1 2 . filter configuration 0 register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x28 filtcon0 [15:8] sinc3_map0 r eserved enhfilten0 enhfilt0 0x0507 rw [7:0] r eserved order0 odr0 table 13 . gain configuration 0 register reg. name bits bit s 23:0 reset rw 0x38 gain0 [23:0] gain0[23:0] 0x5xxxx0 rw table 14 . offset configuration 0 register reg . name bits bit s 23:0 reset rw 0x30 offset0 [23:0] offset0[23:0] 0x800000 rw
data sheet ad7177- 2 rev. a | page 23 of 59 gain registers the gain register s are 24- bit register s that hold the gain calibration coefficient for the adc. the gain registers are read /write registers. these registers are configured at power - on with factory calibrated coefficients. therefore, every device has different default coefficients. the default value is automatically overwritten if a system full - scale calibration is initiated by the user or if the gain register is written to by the user. for more information on calibration, see the operating modes section. offset registers the offset register s hold the offset calibration coefficient for the adc. the power - on reset value of the offset register s is 0x800000. the offset register s are 24- bit read/write register s . the power - on reset value is automatically overwritten if an internal or system zero - scale calibration is initiated by the user or if the offset register s are written to by the user. adc mode and interface mode configuration the adc mode register and the interface mode register configure the core peripherals for use by the ad7177 - 2 a nd the mode for the digital interface. adc mode register the adc mode register primarily set s the conversion mode of the adc to either continuous or single conversion. the user can also select the standby and power - down modes, as well as any of the calibra tion modes. in addition, this register contains the clock source select bits and the internal reference enable bits. the reference select bits are contained in the setup configuration registers (see the adc setups section for more information). interface mode register the interface mode register configures the digital interface operation. this register allows the user to control data - word length, crc ena ble, data + status read , and continuous read mode. the details of the adc mode and interface mode registers are shown in table 15 and table 16 , respectively . for more information, see the digital interface section. table 15 . adc mode register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adcmode [15:8] ref_en hide _ delay sing_cyc r eserved d elay 0x8000 rw [7:0] reserved mode clocksel reserved table 16 . interface mode register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x02 ifmode [15:8] reserved alt_sync iostrength reserved dout_reset 0x0000 rw [7:0] contread data_stat reg_check reserved crc_en wl32 reserved
ad7177- 2 data sheet rev. a | page 24 of 59 understanding configuration flexibility the most straightforward implementation of the ad7177 - 2 is to use two differential inputs with adjacent analog inputs and run both of them with the same setup, gain correction, and offset correction register. in this case, the user selects the following differential inputs: ain0/ain1 and ain2/ain3. in figure 46 , the registers shown in black font must be pro - grammed for such a configuration. the registers shown in gray font are redundant in this configuration. programming the gain and offset registers is optional for any use case, as indicated by the dashed lines between the register blocks. an alternative way to implement these two fully differential inputs is by taking advantage of the four available setups. motivation fo r doing this includes having a different speed/noise requirement on each of the differential inputs , or there may be a specific offset or gain correction for each channel. figure 47 shows how each of the differential inputs can use a separate setup, allowing full flexibility in the configuration of each channel. setup config registers channel registers filter config registers offset registers gain registers* select peripheral functions for adc channel select analog input pairs enable the channel select setup 0 select digital filter type and output data rate data output coding reference source input buffers sinc5 + sinc1 sinc3 sinc3 map enhanced 50hz and 60hz gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x28 0x29 0x2a 0x2b 0x38 0x39 0x3a 0x3b 0x30 0x31 0x32 0x33 setupcon3 setupcon0 setupcon2 setupcon1 filtcon3 filtcon0 filtcon2 filtcon1 gain3 gain0 gain2 gain1 offset3 offset0 offset2 offset1 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 ain0 ain1 ain2 ain3 ain4 12912-046 figure 46 . two fully differential inputs, both using a single setup (setupcon0; filtcon0; gain0; offset0) setup config registers filter config registers offset registers gain registers* select peripheral functions for adc channel select digital filter type and output data rate gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x28 0x29 0x2a 0x2b 0x38 0x39 0x3a 0x3b 0x30 0x31 0x32 0x33 setupcon3 setupcon0 setupcon2 setupcon1 filtcon3 filtcon0 filtcon2 filtcon1 gain3 gain0 gain2 gain1 offset3 offset0 offset2 offset1 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 ain0 ain1 ain2 ain3 ain4 channel registers data output coding reference source input buffers sinc5 + sinc1 sinc3 sinc3 map enhanced 50hz and 60hz 12912-047 figure 47 . two fully differential inputs with a setup per channel
data sheet ad7177- 2 rev. a | page 25 of 59 figure 48 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. in this example, one differential input and two single - ended inputs a re required. the single - ended inputs are the ain2/ain4 and ain3/ain4 combinations. the differential input pair is ain0/ain1and uses s etup 0. the two single - ended input pairs are set up as diagnostics; therefore, use a separate setup from the differential i nput but share a setup between them, s etup 1. given that two setups are selected for use, the setupcon0 and setupcon1 registers are programmed as required, and the filtcon0 and filtcon 1 registers are also programmed as required . optional gain and offset co rrection can be employed on a per setup basis by programming the gain0 and gain1 registers and the offset0 and offset1 registers. in the example shown in figure 48 , the ch0 to ch2 registers are used. setting the msb in each of these registers, the ch_en0 to ch_en2 bits , enable s the three combinations via the crosspoint mux. when the ad7177 - 2 converts, the sequencer transitions in ascending sequential order from ch0 to ch1 to ch2 before looping back to ch0 to repeat the sequence. setup config registers filter config registers offset registers gain registers* select peripheral functions for adc channel select analog input parts enable the channel select setup select digital filter type and output data rate gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x28 0x29 0x2a 0x2b 0x38 0x39 0x3a 0x3b 0x30 0x31 0x32 0x33 setupcon3 setupcon0 setupcon2 setupcon1 filtcon3 filtcon0 filtcon2 filtcon1 gain3 gain0 gain2 gain1 offset3 offset0 offset2 offset1 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 ain0 ain1 ain2 ain3 ain4 channel registers data output coding reference source input buffers sinc5 + sinc1 sinc3 sinc3 map enhanced 50hz and 60hz 12912-048 figure 48 . mixed differential and single - ended configuration using multiple shared setups
ad7177- 2 data sheet rev. a | page 26 of 59 circuit description buffered analog input the ad7177 - 2 has true rail - to - rail , integrated , precision unity - gain buffers on both adc analog inputs. the buffers provide the benefit of giving the user high input impedance with only 30 na typical input current , allowing high impedance sources to be connected directly to the analog inputs . the buffers fully drive the internal adc sw itc h capacitor sampling network , simplifying the analog front - end circuit requirements whil e consuming a very efficient 2.9 ma typical per buffer . each analo g input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. the 1/f noise profile of the adc and buffer combined is shown in figure 49. 1 1000 100 10 amplitude (db) frequency (hz) ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 12912-300 figure 49 . shorted input fft (analog input buffers enabled) the analog input buffers do not suffer from linearity degradation when operating at the rails , unlike many discrete amplifiers. when operating at or close to the av dd1 and avss supply rails , there is an increase in input current. this increase is most notable at higher temperatures. figure 38 and figure 39 show the analog input current for various conditions. with the analog input buffers disabled , the average input current to the ad7177 - 2 changes linearly with the differential input voltage at a rate of 48 a / v. crosspoint multiplex er there are five analog input pins: ain0, ain1, ain2, ain3, and ain4. each of these pins connects to the internal crosspoint multiplexer. the crosspoint multiplexer enables any of these inputs to be configured as an input pair, either single - ended or fully differential. the ad7177 - 2 can have up to four active channels. when more than one channel is enabled, the channels are automatically sequenced in order from the lowest enabled channel number to the highest enabled channel number . the output of the multiplexer is connected to the input of the integrated true rail - to - rail bu ffers. these can be bypassed and the multiplexer output can be directly connected to the switched - capacitor input of the adc. the simplified analog input circuit is shown in figure 50. ain0 ain1 a vdd1 a vss a vss a vss a vdd1 a vss ain2 a vdd1 ain4 a vdd1 ain3 a vdd1 a vss ?1 cs1 cs2 +in ?in ?2 ?2 ?1 12912-056 figure 50 . simplified analog input circuit the cs1 and cs2 capacitors each have a magnitude in the order of a number of picofarads. this capacitance is the combination of both the sampling capac itance and the parasitic capacitance. fully differential inputs because the ain0 to ain4 analog inputs are connected to a crosspoint multiplexer, any combination of signals can be used to create an analog input pair. th e crosspoint multiplexer allows the user to select two fully differential inputs or four single - ended inputs. if two fully differential input paths are connected to the ad7177 - 2 , using ain0/ain1 as one differential input pair and ain2/ain3 as the second differential input pair is recommended. this is due to the relative locations of these pins to each other. decouple a ll analog inputs to avss. single - ended inputs the user can also choose to measure four different single - ended analog inputs. in this case, each of the analog inputs is converted as the difference between the single - ended input to be meas - ured an d a set analog input common pin. because there is a crosspoint multiplexer, the user can set any of the analog inputs as the common pin. an example of such a scenario is to connect the ain4 pin to avss or to the refout voltage (that is, avss + 2.5 v) and s elect this input when configuring the crosspoint multiplexer. when using the ad71 77- 2 with single - ended inputs, the inl specification is degraded.
data sheet ad7177- 2 rev. a | page 27 of 59 ad7177 - 2 reference the ad7177 - 2 offers the user the option of either supplying an external reference to the ref+ and ref? pins of the device or allowing the use of the internal 2.5 v, low noise, low drift reference. select the reference source to be used by the analog input by setting t he ref_selx bits (bits[5:4]) in the setup configuration registers appropriately. the structure of the setup configuration 0 register is shown in table 17 . the ad7177- 2 defaults on power - up to use the internal 2.5 v reference. extern al reference the ad7177 - 2 has a fully differential reference input applied throug h the ref+ and ref? pins. standard low noise, low drift voltage references, such as the adr445 , adr444 , and adr441 , are recommended for use. apply t he external reference to the ad7177 - 2 reference pins as shown in figure 51. decouple t he out put of any external refere nce to avss. as shown in figure 51 , the adr445 output is decoupled with a 0.1 f capacit or at its output for stability purposes. the output is then connected to a 4.7 f capacitor, which acts as a reservoir for any dynamic charge required by the adc, and followed by a 0.1 f decoupling capacitor at the ref+ input. this capacitor is placed as close as possible to the ref+ and ref? pins. the ref? pin is connected directly to the avss potential. on power - up of the ad7177 - 2 , the internal reference is enabled by default and is output on the refout pin. when an external reference is used instead of the internal reference to supply the ad7177 - 2 , attention must be paid to the output of the refout pin. if the internal reference is not being used elsewhere in th e application, ensure that the refout pin is not hardwired to avss because this draw s a large current on power - up. on power - up , if the internal reference is not being used, write to the adc mode register, disabling the internal reference. this is controlle d by the ref_en bit (b it 15) in the adc mode register, which is shown in table 18. internal reference the ad7177 - 2 includes its own low noise, low drift voltage reference. the internal reference has a 2.5 v output. the internal reference is output on the refout pin after the ref_en bit in the adc mode register is set and is decoupled to avss with a 0.1 f capacitor. the ad7177 - 2 internal reference is enabled by default on power - up and is selected as the reference source for the adc. when using the internal reference, the inl performance is degraded as shown in figure 19. the refout signal is buffered before being output to the pin. the signal can be used externally in the circuit as a common - mode source for external amplifier configurations. 2 3 ref? ref+ 4.7f 0.1f 1 1 1 1 1 0.1f 0.1f 5.5v to 18v adr445 2 5v vref AD7177-2 1 all decoupling is to avss. 2 any of the adr440/adr441/adr443/adr444/adr445 family of references can be used. the adr444 and adr441 both enable reuse of the 5v analog supply needed for avdd1 to power the reference v in . 12912-159 figure 51 . external reference adr445 connected to the ad7177 - 2 reference pins table 17 . setup configuration 0 register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x20 setupcon0 [15:8] r eserved bi_unipolar0 refbuf 0 + refbuf 0 ? ainbuf 0 + ainbuf 0 ? 0x1320 rw [7:0] burnout_en0 reserved ref_sel0 reserved table 18 . adc mode register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adcmode [15:8] ref_en hide_delay sing_cyc reserved delay 0x8000 rw [7:0] r eserved mode clocksel reserved
ad7177- 2 data sheet rev. a | page 28 of 59 buffered reference i nput the ad7177 - 2 has tru e rail - to - rail, integrated, precision unity - gain buffers on both ad c reference inputs. the buffers provide the benefit of giving the user high input impedance and allow high impedance external sources to be directly connected to the reference inputs. the integrated reference buffers can fully drive the internal reference switch capacitor sampling network, simplifying the reference circuit requirements while consuming a very efficient 2.9 ma typical per buffer. each reference input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f n oise of the buffer. when using an external reference , such as the adr445 , adr444 , and adr441 , these buffers are not required because these references, with proper decoupling, can drive the reference inputs directly. c lock source the ad7177 - 2 uses a nominal master clock of 16 mhz. the ad7177 - 2 can source its sampling clock from one of three sources : ? internal oscillator ? external crystal ? external clock source all output data rates listed in th is data sheet relate to a master clock rate of 16 mhz. using a lower clock frequency from, for instance, an external source scale s any listed data rate proportion - ally. to achieve the specified data rates, particularly rates for the rejection of 50 hz and 60 hz, use a 16 mhz clock . the source of the master clock is selected by setting the clocksel bits (bits[3:2]) in the adc mode register as shown in table 18 . the default operation on power - up and reset of the ad7177 - 2 is to operate w ith the internal oscillator. it is possible to fine tune the output data rate and filter notch at low output data rates using the s inc3_ m ap x bit . see the sinc3 filter section for more information. internal oscillator the internal oscillator runs at 16 mhz and can be used as the adc master clock. it is the default clock source for the ad7177 - 2 and is specified with an accuracy of 2.5%. there is an option to allow the internal clock oscillator to be output on the xtal2/clkio pin. the clock output is driven to the iovdd logic level. use of this option can affect the dc performance of the ad7177 - 2 due to the disturbance intro - duced by the output driver. the extent to which the performance is affected depends on the iovdd voltage supply. higher iovdd voltages create a wider logic output swing fro m the driver and affect performance to a greater extent. this effect is further exaggerated if the iostrength bit is set at higher iovdd levels (see table 28 for more information). external crystal if higher precision, lower jitter clock sources are required, the ad7177 - 2 can use an external crystal to generate the master clock. the crystal is connected to the xtal1 and xtal2 /clkio pins. a recommended crystal for use is the fa - 20h , a 16 mhz, 10 ppm, 9 pf crystal from epson - toyocom , that is available in a surface - mount package. as shown in figure 52, insert two capacitor s from the traces connecting the crystal to the xtal1 and xtal 2/clkio pins. these capacitors allow circuit tuning. connect these capacitors to the dgnd pin. the value for these capacitors depends on the length and capacitance of the trace connections between the crystal and the xtal1 and xtal2/ clkio pins. therefore, the values of these capacitors differ depending on the printed circuit board ( pcb ) l ayout and the crystal employed. 9 10 cx1 cx2 xtal1 xtal2/clkio *decouple to dgnd. AD7177-2 * * 12912-160 figure 52 . external crystal connections the external crystal circuitry can be sensitive to the sclk edges , depending on sclk frequency, iovdd voltage, crystal circuitry layout , and the crystal used . during crystal startup , any disturbances caused by the slck edges may cause double edges on the crystal input , resulting in invalid conversions until the crystal v oltage has reached a high enough level such that any interference from the sclk edges is insufficient to cause double clocking. this double clocking can be avoided by ensuring that the crystal circuitry has reached a sufficient voltage level after startup before applying any sclk signal. due to the nature of the crystal circuitry , it is recommended that empirical tes ting of the circuit b e performed under the required conditions, with the final pcb layout and crystal, to ensure correct operation. external cl ock the ad7177 - 2 can also use an externally supplied clock. in systems where this is desirable, the external clock is routed to the xtal2/clkio pin. in this configuration, the xtal2/clkio pin accepts the externally sourced clock and routes it to the modulator. the logic level of this clock input is defined by the voltage applied to the iovdd pin.
data sheet ad7177- 2 rev. a | page 29 of 59 digital filters the ad7177 - 2 has three flexible filter options to allow optimiza - tion of nois e, settling time, and rejection , as follows: ? sinc5 + s inc1 filter ? sinc3 filter ? enhanced 50 hz and 60 hz rejection filters sinc1 sinc5 sinc3 50hz and 60hz postfilter 12912-058 figure 53 . digital filter block diagram the filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. each channel can use a different setup an d , therefore , a different filter and output data rate . see the register details section for more information. sinc5 + sinc1 filter the s inc5 + s inc1 filter is targeted at multiplexed applications and achieves single cycle settling at output data rates of 10 ksps and lower. the s inc5 block output is fixed at the maximum rate of 10 ksps , and the s inc1 block output data rate can be varied to control the final adc output data rate. figure 54 shows the frequency domain response of the s inc5 + s inc1 filter at a 50 sps odr . the s inc5 + s inc 1 filter has a slow roll - off over frequency and narrow notches. 0 ?120 0 150 100 50 filter gain (db) frequency (hz) ?100 ?80 ?60 ?40 ?20 12912-059 figure 54 . sinc5 + sinc1 filter response at 50 sps odr the odr with the accompanying settling time and rms noise for the s inc5 + s inc1 filter are shown in table 19 and table 20. sinc3 filter the s inc3 filter achieves the best single - channel noise performance at lower rates and is, therefore, most suitable for single - channel applications. the s inc3 filter always has a settling time , t settle , equal to t settle = 3/ output data rate figure 55 shows the frequency domain filter response for the sinc3 filter. the sinc3 filter has good roll - off over frequency and has wide notches for g ood notch frequency rejection. 0 ?120 0 15 0 10 0 5 0 f i lter g a i n (d b ) f r eq u enc y (h z) ?100 ?80 ?60 ?40 ?20 ?110 ?90 ?70 ?50 ?30 ?10 12912-060 figure 55 . sinc3 filter response the odr with the accompanying settling time and rms noise for the sinc3 filter are shown in table 21 and table 22 . it is possible to finely tune the output data rate for the sinc3 filter by setting the sinc3_map x bit s in the filter configuration register s . if this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. all other options are eliminated. the data rate when on a single channel can be calcul ated using the following equation: 4:0] filtconx[1 f rate data output mod = 32 where: f mod is the modulator rate (mclk/2) and is 8 mhz for a 16 mhz mclk . filtconx[14:0] are the contents on the filter configuration register s excluding the msb. for example, an output data rate of 50 sps can be achieved with sinc3_map x enabled by setting the filtconx[14:0] bits to a value of 5000.
ad7177- 2 data sheet rev. a | page 30 of 59 single cycle settlin g the ad7177 - 2 can be configured by setting the sing_cyc bit in the adc mode register so that only fully settled data is output, effectively putting the adc into a single cycle settling mode. this mod e achieves single cycle settling by reducing the output data rate to be equal to the settling time of the adc for the selected output data rate. this bit has no effect with the sinc5 + sinc1 filter at output data rates of 10 ksps and lower. figure 56 shows a step on the analog input with this mode disabled and the sinc3 filter selected. the analog input requires at least three cycles after the step change for the output to reach the final settled value. 1/odr analog input fully settled adc output 12912-061 figure 56 . step input without single cycle settling figure 57 shows the same step on the analog input but with single cycle settling enabled. the analog input requires at least a single cycle for the output to be full y settled. the output data rate, as indicated by the rdy signal, is reduced to equal the settling time of the filter at the selected output data rate. t settle analog input fully settled adc output 12912-062 figure 57 . step input with single cycle settling table 19. output data rate , settling time, and noise using the sinc5 + sinc1 filter with input buffers disabled default output data rate (sps); sing_cyc = 0 and single channel enabled 1 output data rate (sps/channel); sing_cyc = 1 or with multiple channels enabled 1 settling ti me 1 notch frequency (hz) noise (v rms) effective resolution with 5 v reference (bits) dynamic range with 5 v reference (db) noise (v p - p) 2 peak - to - peak resolution with 5 v reference (bits) 10,000 10,000 100 s 11,905 2.5 21.9 123 18.3 19.1 5000 5000 200 s 5435 1.7 22.5 126.4 12 19.7 2500 2500 400 s 2604 1.2 23 129.4 8.2 20.2 1000 1000 1.0 ms 1016 0.77 23.6 133.2 5.2 20.9 500 500.0 2.0 ms 504 0.57 24.3 135.9 3.2 21.6 397.5 397.5 2.516 ms 400.00 0.5 24.4 137 3 21.7 200 200.0 5.0 ms 200.64 0.36 25 139.8 2 22.3 100 100 10 ms 100.16 0.25 25.6 143 1.3 22.9 59.92 59.92 16.67 ms 59.98 0.19 25.8 145.4 1.1 23.1 49.96 49.96 20.016 ms 50.00 0.18 26 145.9 0.95 23.3 20 20.00 50.0 ms 20.01 0.11 26.7 150.1 0.6 24 16.66 16.66 60.02 ms 16.66 0.1 26.7 151 0.45 24.1 10 10.00 100 ms 10.00 0.08 26.8 152.9 0.4 24.2 5 5.00 200 ms 5.00 0.07 27.3 154.1 0.34 24.6 1 the settling time is rounded to the nearest microsecond. this is reflected in the output data rate and channel switching rate . channel switching rate = 1 settling time. 2 measurement taken using 1000 samples.
data sheet AD7177-2 rev. a | page 31 of 59 table 20. output data rate, settling time, and noise usin g the sinc5 + sinc1 filter with input buffers enabled default output data rate (sps); sing_cyc = 0 and single channel enabled 1 output data rate (sps/channel); sing_cyc = 1 or with multiple channels enabled 1 settling time 1 notch frequency (hz) noise (v rms) effective resolution with 5 v reference (bits) dynamic range with 5 v reference (db) noise (v p-p) 2 peak-to-peak resolution with 5 v reference (bits) 10,000 10,000 100 s 11,905 3 21.7 121.4 23 18.7 5000 5000 200 s 5435 2.1 22.2 124.5 16 19.3 2500 2500 400 s 2604 1.5 22.7 127.4 10 19.9 1000 1000 1.0 ms 1016 0. 92 23.4 131.7 5.7 20.7 500 500.0 2.0 ms 504 0. 68 23.8 134.3 3.9 21.3 397.5 397.5 2.516 ms 400.00 0.6 24.1 135.4 3.7 21.4 200 200.0 5.0 ms 200.64 0.43 24.8 138.3 2.2 22.1 100 100 10 ms 100.16 0.32 25.2 140.9 1.7 22.5 59.92 59.92 16.67 ms 59.98 0.23 25.7 143.7 1.2 23 49.96 49.96 20.016 ms 50.00 0.2 26 144.9 1 23.3 20 20.00 50.0 ms 20.01 0.14 26.4 148 0.75 23.7 16.66 16.66 60.02 ms 16.66 0.13 26.6 148.7 0.66 23.9 10 10.00 100 ms 10.00 0.1 26.7 151 0.47 24.1 5 5.00 200 ms 5.00 0. 07 26.7 154.1 0.32 24.6 1 the settling time is rounded to the nearest microsecond. this is reflected in the output data rate and channel switching rate. channel switching rate = 1 settling time. 2 measurement taken using 1000 samples. table 21. output data rate, settling time, and noise using the sinc3 filter with input buffers disabled default output data rate (sps); sing_cyc = 0 and single channel enabled 1 output data rate (sps/channel); sing_cyc = 1 or with multiple channels enabled 1 settling time 1 notch fre- quency (hz) noise (v rms) effective resolution with 5 v reference (bits) dynamic range with 5 v reference (db) noise (v p--p) 2 peak-to-peak resolution with 5 v reference (bits) 10,000 3333 300 s 10,000 1.8 22.4 125.9 14 19.4 5000 1667 6 s 5000 1.3 22.9 128.7 9.5 20 2500 833 1.2 ms 2500 0.91 23.4 131.8 6 20.7 1000 333.3 3 ms 1000 0.56 24 136 3.9 21.3 500 166.7 6 ms 500 0.44 24.6 138.1 2.5 21.9 400 133.3 7.5 ms 400 0.4 24.8 138.9 2.3 22.1 200 66.7 15 ms 200 0.25 25.5 143 1.4 22.8 100 33.33 30 ms 100 0.2 26 144.9 1 23.3 60 19.99 50.02 ms 59.98 0.13 26.3 148.7 0.8 23.6 50 16.67 60 ms 50 0.13 26.5 148.7 0.7 23.8 20 6.67 150 ms 20 0.08 26.9 152.9 0.42 24.2 16.67 5.56 180 ms 16.67 0.07 27 154.1 0.37 24.3 10 3.33 300 ms 10 0.06 27.1 155.4 0.28 24.4 5 1.67 600 ms 5 0.05 27.5 157 0.21 24.8 1 the settling time is rounded to the nearest microsecond. this is reflected in the output data rate and channel switching rate. channel switching rate = 1 settling time. 2 measurement taken using 1000 samples.
ad7177- 2 data sheet rev. a | page 32 of 59 table 22 . output data rate, settling time, and noise using the sinc3 filter with input buffers en abled default output data rate (sps); sing_cyc = 0 and single channel enabled 1 output data rate (sps/channel); sing_cyc = 1 or with multiple channels enabled 1 settling time 1 notch frequency (hz) noise (v rms) effective resolution with 5 v reference (bits) dynamic range with 5 v reference (db) noise (v p - p) 2 peak - to - peak resolution with 5 v reference (bits) 10,000 3333 300 s 10,000 2.1 22.2 124.5 16 19.3 5000 1667 6 s 5000 1.5 22.7 127.4 11 19.8 2500 833 1.2 ms 2500 1.1 23.1 130.1 7 20.4 1000 333.3 3 ms 1000 0.71 23.7 133.9 4.5 21.1 500 166.7 6 ms 500 0.52 24.4 136.6 3 21.7 400 133.3 7.5 ms 400 0.41 24.5 138.7 2.7 21.8 200 66.7 15 ms 200 0.32 25.1 140.9 1.8 22.4 100 33.33 30 ms 100 0.2 25.7 144.9 1.2 23 60 19.99 50.02 ms 59.98 0.17 25.8 146.4 1.1 23.1 50 16.67 60 ms 50 0.15 26.2 147.4 0.83 23.5 20 6.67 150 ms 20 0.13 26.7 148.7 0.61 24 16.67 5.56 180 ms 16.67 0.12 26.8 149.4 0.6 24.1 10 3.33 300 ms 10 0.1 26.9 151 0.55 24.2 5 1.67 600 ms 5 0.08 27.2 152.9 0.35 24.5 1 the settling time is rounded to the nearest microsecond. this is reflected in the output data rate and channel switching rate. c hannel switch ing rate = 1 settling time. 2 measurement taken using 1000 samples.
data sheet ad7177- 2 rev. a | page 33 of 59 enhanced 50 hz and 6 0 hz rejection filte rs the enhanced filters are designed to provide rejection of 50 hz and 60 hz simultaneously and to allow the user to trade off settling time and rejection. these filters can operate up to 27.27 sps or can reject up to 90 db of 50 hz 1 hz and 60 hz 1 hz interference. the se filters are realized by post filtering t he output of the sinc5 + sinc1 filter. for this reason, the sinc5 + sinc1 filter must be selected when using the enhanced filters to achieve the specified settling time and noise performance . table 23 shows the output data rates with the accompanying settling time, rejection, and rms noise. figure 58 to figure 65 show the frequency domain plots of the responses from the enhanced filters. table 23 . enhanced filters output data rate, noise, settling time, and rejection using the enhanced filters output data rate (sps) settling time (ms) simultaneous rejection of 50 hz 1 hz and 60 hz 1 hz (db) 1 noise (v rms) peak - to - peak resolution (bits) comments input buffers disabled 27.27 36.67 47 0.22 22.7 see figure 58 and figure 61 25 40.0 62 0.2 22.9 see figure 59 and figure 62 20 50.0 85 0.2 22.9 see figure 60 and figure 63 16.667 60.0 90 0.17 23 see figure 64 and figure 65 input buffers enabled 27.27 36.67 47 0.22 2 2 .7 see figure 58 and figure 61 25 40.0 62 0. 22 22.7 see figure 59 and figure 62 20 50.0 85 0.21 22.8 see f igure 60 and figure 63 16.667 60.0 90 0.21 22.8 see figure 64 and figure 65 1 maste r clock = 16.00 mhz.
ad7177- 2 data sheet rev. a | page 34 of 59 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 12912-063 figure 58 . 27.27 sps odr, 36.67 ms settling time 0 ?100 0 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 600 100 200 300 400 500 12912-065 figure 59 . 25 sps odr, 40 ms settling time 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 12912-067 figure 60 . 20 sps odr, 50 ms settling time 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 12912-064 figure 61 . 27.27 sps odr, 36.67 ms settling time at 50 hz/60 hz 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 12912-066 figure 62 . 25 sps odr, 40 ms settling time at 50 hz/60 hz 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 12912-068 figure 63 . 20 sps odr, 50 ms settling time at 50 hz/60 hz
data sheet ad7177- 2 rev. a | page 35 of 59 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 12912-069 figure 64 . 16.667 sps odr, 60 ms settling time 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 12912-070 figure 65 . 16.667 sps odr, 60 ms settling time at 50 hz/60 hz
ad7177- 2 data sheet rev. a | page 36 of 59 operating modes the ad7177 - 2 has a number of operating modes that can be set from the adc m ode r egister and interface mode register (s ee table 27 and table 28). the se modes are as follows and are descri bed in the following sections : ? continuous c onversion m ode ? continuous r ead m ode ? single c onversion m ode ? standby m ode ? power - d own m ode ? calibration m odes ( three modes ) continuous conversio n mode continuous conversion is the default power - up mode. the ad7177 - 2 converts continuously, and the rdy bit in the status register goes low each time a conversion is complete. if cs is low, the rdy output also goes low when a conversion is complete. to read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. when the data - word has been read from the data register, the dout/ rdy pin goes high. the user can read this register additional times, if required. however, the user must ensure that the data register is not being accessed at the completion of the next conversion; otherwise , the new conversion word is los t. when several channels are enabled, the adc automatically sequences through the enabled channels, performing one conversion on each channel. when all channels have been converted, the sequence starts again with the first channel. the channels are converted in order from lowest enabled channel to highest enabled channel. the data register is updated as soon as each conversion is available. the rdy output pulses low each time a conversion is available. the user can then read the c onversi on while the adc converts the next enabled channel . if the data_stat bit in the interface mode register is set to 1, the contents of the status register, along with the conversion data, are output each time the data register is read. the status register in dicates the channel to which the conversion corresponds. din sclk dout/rdy cs 0x44 0x44 data data 12912-071 figure 66 . continuous conversion mode
data sheet ad7177- 2 rev. a | page 37 of 59 continuous read mode in continuous read mode, it is not required to wri te to the communications register before reading adc data; apply only the req uired number of sclk pulses after rdy goes low to indicate the end of a conversion. when the conversion is read, rdy returns high until the next conversion is available. in this mode, the data can be read only once. the user must also ensure that the data - word is read before the next conversion is complete. if the user has not read the conversion before the completion o f the next conversion or if insufficient serial clocks are applied to the ad7177 - 2 to read the data - word , the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output serial register. the adc must be configured for continuous conversion mode to use continuous read mo de. to enable continuous read mode, set the contread bit in the interface mode register. when this bit is set, the only serial interface operations possible are reads from the data register. to exit con - tinuous read mode, issue a dummy read of the adc data register command (0x44) while the rdy output is low. alternatively, apply a software reset, that is, 64 sclk pulses with cs = 0 and din = 1. this resets the adc and all register contents. these are the only co mmands that the interface recognizes after it is placed in continuous read mode. hold din low in continuous read mode until an instruction is to be written to the device. if multiple adc channels are enabled, each channel is output in turn, with the stat us bits being appended to the data if data_stat is set in the interface mode register. the status register indicates the channel to which the conversion corresponds. din sclk dout/rd y cs 0x02 data data data 0x0080 12912-072 figure 67 . continuous read mode
ad7177- 2 data sheet rev. a | page 38 of 59 single conversion mo de in single conversion mode, the ad7177 - 2 performs a single conversion and is placed in standby mode after the conve rsion is complete. the rdy output goes low to indicate the completion of a conversion . when the data - word has been read from the data register, the dout/ rdy pin goes high. the data register can be read several times, if required, even when the dout/ rdy pin has gone high. if several channels are enabled, the adc automatically sequences through the enabled channels and performs a conversion on each channel. when a conversion is started, the dout/ rdy pin goes high and remains high until a valid conversion is available and cs is low. as soon as the conversion is available, the rdy output goes low. the adc then selects the next channel and begins a conversion. the user can read the present conversion while the next conversion is being performed. as soon as the next conversion is complete, the data register is updated; therefore, the user has a limite d period in which to read the conversion. when the adc has performed a single conversion on each of the selected channels, it returns to standby mode. if the data_stat bit in the interface mode register is set to 1, the contents of the status register, alo ng with the conversion, are output each time the data register is read . the two lsbs of the status register indicate the channel to which the conversion corresponds . din sclk dout/rdy cs 0x01 0x44 data 0x8010 12912-073 figure 68 . single conversion mode
data sheet ad7177- 2 rev. a | page 39 of 59 standby and power - down modes in standby mode, most blocks are powered down. the ldos remain active so that registers maintain their contents. the internal reference remains active if enabled, and the crystal oscillator remains active if selected. to power down the reference in standby mode, set the ref_en bit in the adc mode regi s ter to 0. to power down the clock in standby mode, set the clocksel bits in the adc mode register to 00 (internal oscillator). in power - down mode, all blocks are powered down, including the ldos. all registers lose their contents, and the gpio x outputs are placed in three - state. to prevent accidental entry to power - down mode, the adc must first be placed in standby mode. exiting power - down mode requires 64 sclk pul ses with cs = 0 and din = 1, that is, a serial interface reset. a delay of 500 s is recommended before issuing a subsequent serial interface command to allow the ldo to power up. figure 15 shows the internal reference settling time after returning from standby mode (setting ref_en = 0 and then 1) and returning from power - down. calibration the ad7177 - 2 allows a two - point calibration to be performed to eliminate any offset and gain errors. three calibration m odes eliminate the se offset and gain errors on a per setup basis , as follows : ? internal zero - scale calibration mode ? system zero - scale calibration mode ? system full - scale calibration mode there is no internal full - scale calibration mode b e cause this is calibrated in the factory at the time of production . only one channel can be active during calibration. after each conversion, the adc conversion result is scaled using the adc calibration registers before being written to the data register. the default value of the offset register is 0x800000, and the nominal value of the gain register is 0x555555. the calibration range of the adc gain is from 0.4 v ref to 1.05 v ref . the following equations show the calculations that are used for 24- bit data o utput . in unipolar mode, the ideal relationship that is, not taking into account the adc gain error and offset error is as follows: ( ) ? ? ? ? ? ? ? ? ? ? = gain offset v v data ref in in ipolar moe te ieal relationsip tat is not tain into aount te dc ain error an offs et error is as follos: ( ) + ? ? ? ? ? ? ? ? ? ? = gain offset v v data ref in to start a aliration rite te relevant value to te moe its in te dc moe reister te dot rd pin an te rd it in te status reister o i en t e aliration initiates en te aliration is omplete te ontents of te orrespon in offset or ain reister are upate te rd it i n te status reister is reset an te rd output pin returns lo if cs is lo an te d1 reverts to stan moe durin an internal offset aliration te selete positive analo input pin is isonnete an ot moulator inputs are onnete internall to te selete neative analo input pin for tis reason it is neessar to ensure tat te voltae on te selete neative analo input pin oes not exee te alloe limits an is free from exessive noise an interferene sstem alirations oever expet te sstem ero sale offset an sstem full sale ain voltaes to e applie to te dc pin s efore initiatin te aliration moes s a result errors external to te dc are remove from an operational point of vie treat a aliration lie anoter dc onversion n offset aliration if reuire must alas e performe efore a full s ale aliration set te sstem softare to monitor te rd it in te status reister or te rd output to etermine te en of a aliration via a pollin seuene or an interrupt riven routine ll alira tions reuire a time eual to te settlin time of te selete filter an output ata rate to e omplete n internal offset aliration sstem ero sale aliration an sstem full sale aliration an e performe at an output ata rate sin lo er output ata rates results in etter aliration aura an is aurate for all output ata rates ne offset aliration is reuire for a iven annel if te referene soure for tat annel is ane te offset error is tpiall 40 v an a n offset aliration reues te offset error to te orer of te noise te ain error is fator alirate at amient temperature folloin tis aliration te ain error is tpiall ppm of fsr te d1 provies te user it aess to te on ip aliration reisters alloin te miroproessor to rea te alirat ion oeffiients of te evie an to rite its on aliration oeffiients rea or rite of te offset an ain reisters an e performe at an time exept urin an internal or self aliration
ad7177- 2 data sheet rev. a | page 40 of 59 digital interface the programmable functions of the ad7177 - 2 are controlled via the spi serial interface. the serial interface of the ad7177 - 2 consists of four signals: cs , din, sclk, and dout/ rdy . the din input is used to transfer data into the on - chip registers, and the dout output is used to access data from the on - chip registers. sclk is the serial clock input for the device, and all data transfers (either on the din i nput or on the dout output ) occur with respect to the sclk signal. the dout/ rdy pin also functions as a data ready signal, with the output going low if cs is low when a new data - word is available in the data register. the rdy output is reset high when a read operation from the data register is complete. the rdy output also goes high before updating the data register to indicate when not to read from th e device to ensure that a data read is not attempted while the register is being updated. take care to avoid reading from the data register when the rdy output is about to go low. the best method to ensure that no data read occurs is to always monitor the rdy output ; start reading the data register as soon as the rdy output goes low; and ensure a sufficient sclk rate, such that the read is complete before the next conversion result . cs is used to select a device. it can be used to decode the ad71 77- 2 in systems where several components are connected to the serial bus. figure 2 and figure 3 show timing diagrams for interfacing to the ad7177 - 2 using cs to decode the device . figur e 2 shows the timing for a read operation from the ad7177 - 2 , and figure 3 shows the timing for a write operation to the ad7177 - 2 . it is possible to read from the data register several times even though t he rdy output returns high after the first read operation. however, care must be taken to ensure that the read operations are completed before the next output update occurs. in continuous read mode, the data register can be read only once. the serial interface can operate in 3 - wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy pins are used to communicate with the ad7177 - 2 . the end of the conversion can also be monitored using the rdy bit in the status register. the ad7177 - 2 can be reset by writing 64 sclks with cs = 0 and din = 1. a r eset returns the interface to the state in which it expects a write to the communications register. this operation resets the contents of all registers to their power - on values. following a reset, allow a period of 500 s before addressing the serial inter face. checksum protection the ad7177 - 2 has a checksum mode that can be used to improve interface robustness. using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. if an error occurs during a register write, the crc_error bit is set in the status register. however, to ensure that the register write is successful, read back the register and verify the checksum . for crc checksum calculations during a write operation, the following polynomial is always used: x 8 + x 2 + x + 1 during read operations, the user can select between this polynomial and a sim pler exclusive or ( xor ) function. the xor function requires less time to process on the host microcontroller than the polynomial - based checksum. the crc_en bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple xor check. the checksum is appended to the end of each read and write transaction. the checksum calculation for the write transaction is calculated using the 8 - bi t command word and the 8 - bit to 24- bit data. for a read transaction, the checksum is calculated using the command word and the 8 - bit to 32 - bit data output. figure 69 and figure 70 show spi write and read transactions, respectively. 8-bit command 8-bit crc up t o 24-bit input cs data crc cs din sclk 12912-074 figure 69 . spi write transaction with crc 8-bit command 8-bit crc up t o 40-bit output cmd data crc cs din sclk dout/ rd y 12912-075 figure 70 . spi read transaction with crc if checksum protection is enabled when c ontinuous read mode is active, an implied read data command of 0x44 before every data transmission must be accounted for when calculating the ch ecksum value. this implied read data command ensures a nonzero checksum value even if the adc data equals 0x000000.
dat a sheet ad7177- 2 rev. a | page 41 of 59 crc calculation polynomial the checksum, which is eight bits wide, is generated using the polynomial x 8 + x 2 + x + 1 to generate the che cksum, the data is left shifted by eight bits to create a number ending in eight logic 0s. the polynomial is aligned so that its msb is adjacent to the leftmost logic 1 of the data. an xor function is applied to the data to produce a new, shorter number. t he polynomial is again aligned so that its msb is adjacent to the leftmost logic 1 of the new result, and the proce - dure is repeated. this process repeat s until the original data is reduced to a value less than the polynomial. this is the 8 - bit checksum. example of a polynomial crc calculation 24- bit word: 0x654321 (eight command bits and 16 - bit data) an example of generating the 8 - bit checksum using the polynomial - based checksum is as follows: initial value 011001010100001100100001 01100101010000110010000100000000 left shifted eight bits x 8 + x 2 + x + 1 = 100000111 polynomial 100100100000110010000100000000 xor result 100000111 polynomial 100011000110010000100000000 x or result 100000111 polynomial 11111110010000100000000 xor result 100000111 polynomial value 1111101110000100000000 xor result 100000111 polynomial value 111100000000100000000 xor result 100000111 polynomial value 11100111000100000000 xor result 100000111 polynomial value 11 00100100100000000 xor result 100000111 polynomial value 100101010100000000 xor result 100000111 polynomial value 101101100000000 xor result 100000111 polynomial value 1101011000000 xor result 100000111 polynomial value 101 010110000 xor result 100000111 polynomial value 1010001000 xor result 100000111 polynomial value 10000110 checksum = 0x86
ad7177- 2 data sheet rev. a | page 42 of 59 xor calculation the checksum, which is 8 bits wide, is generated by splitting the data into bytes and then performing an xor of the bytes. example of an xor calculation 24- bit word : 0x654321 (eight command bits and 16 - bit data) using the previous example of a polynomial crc calculation , d ivide the data into three bytes: 0x65, 0x43, and 0x21 . 01100101 0x65 01000011 0x43 00100110 xor result 00100001 0x21 00000111 crc
dat a sheet ad7177- 2 rev. a | page 43 of 59 integrated functions the ad7177 - 2 has integrated functions that improve the usefulness of a number of applications as well as serve diagnostic purposes in safety conscious applications . general - purpose i/o the ad 7177- 2 has two general - purpose digital input/output pins: gpio0 and gpio1. the y are enabled using the ip_en0/ip_en1 bits or the op_en0/op_en1 bits in the gpiocon register. when the gpio0 or gpio1 pin is enabled as an input, the logic level at the pin is co ntained in the gp_ data0 or gp_ data1 bit, respec - tively. when the gpio0 or gpio1 pin is enabled as an output, the gp_data0 or gp_data1 bits, respectively, determine the logic level output at the pin. the logic levels for these pins are referenced to av dd 1 a nd avss; therefore, outputs have an amplitude of 5 v. the sync / error pin can also be used as a general - purpose output. when the err_en bits in the gpiocon register are set to 11, the sync / error pin operates as a general - purpose output. in this configuration, the err_dat bit in the gpiocon register determines the logic level output at the pin. the logic level for the pin is referenced to iovdd and dgnd . both gpios and the sync / error pin, when set as general - purpose output s, have an active pull - up circuit . external multiplexer control if an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlle d via the ad7177 - 2 gpio x pins. with the mux_io bit, the gpio x timing is controlle d by the adc; therefore, the channel change is synchronized with the adc, eliminating any need for external synchronization. delay it is possible to insert a programmable delay before the ad7177 - 2 begins to tak e samples. this delay allows an external amplifier or multiplexer to settle and can alleviate the specification requirements fo r the external amplifier or multiplexer. e ight programmable settings , ranging from 0 s to 1 ms , can be set using the delay bits in the adc m ode r egister ( register 0x01, bits [ 10:8 ] ). if a delay greater than 0 s is selected and the hide_delay bit in the adc m ode r egister is set to 0 , this delay is added to the conversion time , regardless of the selected output data rate. when using the s inc5 + s inc1 filter , it is possible to hide this delay such that the output data rate remain s the same as the output dat a rate without the delay enabled. if the hide_delay bit is set to 1 and the selected delay is less than half of the conversion time , the delay can be absorbed by reducing the number of averages the digital filter perform s, which keeps the conversion time t he same but ca n affect the noise performance. the effect on the noise performance de pend s on the delay time compared to the conversion time. it is possible to absorb the delay only for output data rates less than 10 ksps with the exception of the following four rates , which cannot absorb any delay: 397.5 sps, 59.9 2 sps, 49.96 sps , and 16.66 sps. 24- bit /32 - b it conversions by default, the ad7177 - 2 generates 24 - bit conversions. however, the w idth of the conversions can be increased to 32 bits . setting the wl 32 bit in the interface mode register to 1 sets all data conversions to 32 bits. clearing this bit sets the width of the data conversions to 24 bits. the wl 32 bit affects the size of the data register but does not affect the size of the offset or gain registers. if 32 - bit data conversions are enabled at the same time that the da ta_stat bit is set , the adc output s 28 data bits and the four channel bits of the status register for each data read. d out _r eset the serial interface uses a shared dout/ rdy pin. by default , this pin outputs the rdy signal. during a data read , this pin output s the data from the register being read. after the read is complete , the pin revert s to outputting the rdy signal after a short fixed period of time (t 7 ). however, this time may be too short for some micro controllers and can be extended until the cs pin is brought high by setting the dout_reset bit in the i nterface m ode r egister to 1. this means that cs must be used to frame each read operation and compete the serial interface transaction. synchronization normal synchronization when the sync_en bit in the gpiocon register is set to 1, the sync / error pin functions as a synchronization input . the sync input let s the user reset the modulator and the digital filter without affecting any of the setup conditions on the device . this feature lets the user start to gather samples of the analog input from a known point, the rising edge of the sync inpu t . the sync input must be low for at least one master clock cycle to ensure that synchronization occurs. if multiple ad7177 - 2 devices are operated from a common master clock, they can be synchronized so that their analog inputs are sampled simultaneously. this synchronization is normally done after each ad7177 - 2 device has performed its own calibration or has calibration coefficients loaded into its calibration registers. a falling edge on the sync input resets the digital filter and the analog modulator and places the ad7177 - 2 into a consistent known state. while the sync input is low, the ad7177 - 2 is maintained in this known state. on the sync input rising edge, the modulator and filter are taken out of this reset state, and on the next master clock e dge, the device starts to gather input samples again.
ad7177- 2 data sheet rev. a | page 44 of 59 the device is taken out of reset on the master clock falling edge following the sync input low to high transition. therefore, when multiple devices are being synchronized, take the sync input high on the master clock rising edge to ensure that all devices are released on the master clock falling edge. if the sync input is not taken high in sufficient time, a difference of one master clock cycle between the devices is possible ; that is, the instant at which conversions are available differs from device to device by a maximum of one master clock cycle. the sync input can also be used as a start conversion com - mand for a single channel wh en in normal synchronization mode . in this mode, the rising edge of the sync input starts a conversion, and the falling edge of the rdy output indicates when the conversion is complete. the settling time of the filter is required for each data register update. after the conversion is complete , bring the sync input low in preparation for the next conversion start signal. alternate synchronization in alternate synchronization mode, the sync input operates as a start conversion command when several channels of the ad7177 - 2 are enabled. setting the alt_sync bit in the interface mode register to 1 enables an alternate synchronization scheme. when the sync input is taken low, the adc completes the conversion on the current channel, selects the next ch annel in the sequence, and then waits until the sync input is taken high to commence the conversion. the rdy output goes low when the conversion is complete on the current channel, and the data register is updated with the corresponding conversion. therefore, the sync input does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. alternate synchronization mode can be used only when several channels are enabled. it is not recommended to use this mode when a single channel is enabled. error flags the status register contains three error bits adc_error, crc_error, and reg_error that f lag errors with the adc conversion, errors with the crc check, and errors caused by changes in the registers, respectively. in addition, the error output can indicate that an error has occurred. adc_error the adc_error bit in the status r egister flags any errors that occur during the conversion process. the flag is set when an over - range or under range result is output from the adc . the adc also outputs all 0s or all 1s when an undervoltage or overvoltage occurs. this flag is reset only whe n the overvoltage or undervoltage is removed. it is not reset by a read of the data register. crc_error if the crc value that accompanies a write operation does not correspond with the information sent, the crc_error flag is set. the flag is reset as soon as the status register is explicitly read. reg_error th e re g _error flag is used in conjunction with the reg_check bit in the interface mode register. when the reg_check bit is set, the ad7177 - 2 monitors the values in the on - chip registers. if a bit changes, the reg_error bit is set. therefore, for writes to the on - chip registers, set reg_ check to 0. when the registers have been updated, the reg_check bit can be set to 1. the ad7177 - 2 c alculates a checksum of the on - chip registers. if one of the register values has changed, the reg_error bit is set. if an error is flagged, the reg_check bit must be set to 0 to clear the reg_error bit in the status register. the register check function does not monitor the data register, status register, or interface mode register. error input/output when the sync_en bit in the gpiocon register is set to 0 , the sync / error pin functions as an error input/output pin or a general - purpose output pin. the err_en bits in the gpiocon register determine the function of the pin. with err_en is set to 10, the sync / error pin functions as an open - drain error output , error . the three error bits in the status register (adc_error, crc_error, and reg_error) are ored, inverted, and mapped to the error output . therefore, the error output indicates that an error has occurred. the status register must be read to identify the error source. when err_en is set to 01, the sync / error pin functions as an error input , error . the error output of another component can be connected to the ad7177 - 2 error input so that the ad7177 - 2 indicates when an error occurs on either itself or the external component. the value on the error input is inverted a n d o re d with the errors from the adc conversion, and the result is indicated via the adc_error bit in the status register. the value of th e error input is reflected in the err_dat bit in the status register. the error input/output is disabled when err_en is set to 00. when the err_en bits are set to 11, the sync / error pin operates as a general - purpose output. d ata_s tat the contents of the status register can be appended to each con - version on the ad7177 - 2 . this function is useful if several channels are enabled. each time a conversion is output, the contents of the status register are appended. the two lsbs of the status register indicate to which channel the conversion corresponds. in addition, the user can determine if any errors are being flagged by the error bits. if 32 - bit data conversions are
dat a sheet ad7177- 2 rev. a | page 45 of 5 9 enabled at the same time that the data_stat bit is set , the adc output s 28 data bi ts and the four chan nel bits of the status register for each data read. ios trength the serial interface can operate with a power supply as low as 2 v. however, at this low voltage, the dout/ rdy pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board or the sclk frequency is high. the iostrength bit in the interface mode register increases the drive strength of the dout/ rdy pin. internal temp erature sensor the ad7177 - 2 has an integrated temperature sensor. the temperature sensor can be used as a guide for the ambient temperature at which the device is operating. this can be use d for diagnostic purposes or as an indicator of when the applica - tion circuit needs to rerun a calibration routine to take into account a shift in operating temperature. the temperature sensor is selected us ing the crosspoint multiplexer and is selected in the same way as an analog input channel. the temperature sensor requires that the analog input buffers be enabled on both analog inputs. if the buffers are not enabled , selecting the temperature sensor as an input force s the buffers to be enabled during the conversion. to use the temp erature sensor, the first step is to calibrate the device in a known temperature (25c) and take a conversion as a reference point. the tem perature sensor has a nominal sensitivity of 47 0 v/ k ; the difference in this ideal slope and the slope measured can be used to cal ibrate the temperature sensor . the temperature sensor is specified with a 2 c typical accuracy after calibration at 25 c . ca librate t he temperature as follows: 15 . 273 C v 0 47 ) c ( ? ? ? ? ? ? ? ? = result conversion e temperatur
ad7177- 2 data sheet rev. a | page 46 of 59 grounding and layout the analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common - mode voltages. the high common - mode rejection of the device removes common - mode noise on these inputs. the analog and digital su pplies to the ad7177 - 2 are independent and connected to separate pins to minimize coupling between the analog and digital sections of the device. the digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. the digital filter also removes noise from the anal og and reference inputs, provided that these noise sources do not saturate the analog modulator. as a result, the ad7177 - 2 is more immune to noise interference than a conventional high resolution converter. however, because the resolution of the ad7177 - 2 is high and the noise levels from the converter are so low, take car e with regard to grounding and layout. the pcb that houses the adc must be designed s uch that t he analog and digital sections are separated and confined to certain areas of the board. a minimum etch technique is generally best for ground planes because it results in the best shielding. in any layout, the user must consider the flow of currents in th e system, ensuring that the paths for all return currents are as close as possible to the p aths the currents took to reach their destinations . avoid running digital lines under the device because this couples noise onto the die and allow s the analog ground plane to run under the ad7177 - 2 to prevent noise coupling. the power supply line s to the ad7177 - 2 must use as wide a trace as possible to provide low impedance p aths and reduce glitches on the power supply line. shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. avoid crossover of digital and an alog signals. run traces on opposite sides of the board at right angles to each other. this technique reduces the effects of feedthrough on the board. a microstrip technique is by far the best metho d but is not always possible with a double sided board. good decoupling is important when using high resolution adcs. the ad7177 - 2 has th ree power supply pins av dd1, av dd2, and iovdd. the avdd1 and avdd2 pins are referenced to avss, and the iovdd pin is referenced to dgnd. decouple avdd1 and avdd2 with a 10 f capacitor in parallel with a 0.1 f capacitor to avss on each pin. place t he 0.1 f capacitor as close as possible to the device on each supply, ideally right up against the device. decouple iovdd with a 10 f capacitor in parallel with a 0.1 f capacitor to dgnd. decouple all analog inputs to avss. if an external reference is used, de couple the ref+ and ref? pins to avss. the ad7177 - 2 also has two on - board ldo reg ulators one that regulates the avdd2 supply and one that regulates the iovdd supply. for the regcapa pin, it is recommended that 1 f and 0.1 f capacitors to avss be used. similarly, for the regcapd pin, it is recommended that 1 f and 0.1 f capaci - tors to dgnd be used. if using the ad7177 - 2 for split supply operation, a separate pla ne must be used for avss.
data sheet AD7177-2 rev. a | page 47 of 59 register summary table 24. register summary reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] wen r/ w ra 0x00 w 0x00 status [7:0] rdy adc_error crc_error reg_error reserved channel 0x80 r 0x01 adcmode [15:8] ref_en hide_delay sing_cyc reserved delay 0x8000 rw [7:0] reserved mode clocksel reserved 0x02 ifmode [15:8] reserved alt_sync io strength reserved dout_reset 0x0000 rw [7:0] contread data_stat reg_check reserved crc_en wl32 reserved 0x03 regcheck [23:16] register_check[23:16] 0x000000 r [15:8] register_check[15:8] [7:0] register_check[7:0] 0x04 data [31:17] data[31:17] 0x000000 r [23:16] data[23:16] [15:8] data[15:8] [7:0] data[7:0] 0x06 gpiocon [15:8] rese rved mux_io sync_en err_en err_dat 0x0800 rw [7:0] reserved ip_en1 ip_en0 op _en1 op_en0 gp_data1 gp_data0 0x07 id [15:8] id[15:8] 0x4fdx r [7:0] id[7:0] 0x10 ch0 [15:8] ch_en0 reserved setup_ sel0 reserved ainpos0[4:3] 0x8001 rw [7:0] ainpos0[2:0] ainneg0 0x11 ch1 [15:8] ch_en1 reserved setup_ sel1 reserved ainpos1[4:3] 0x0001 rw [7:0] ainpos1[2:0] ainneg1 0x12 ch2 [15:8] ch_en2 reserved setup_ sel2 reserved ainpos2[4:3] 0x0001 rw [7:0] ainpos2[2:0] ainneg2 0x13 ch3 [15:8] ch_en3 reserved setup_ sel3 reserved ainpos3[4:3] 0x0001 rw [7:0] ainpos3[2:0] ainneg3 0x20 setupcon0 [15:8] reserved bi_unipolar0 re fbuf0+ refbuf0- ainbuf0+ ainbuf0? 0x1320 rw [7:0] burnout_en0 reserved ref_sel0 reserved 0x21 setupcon1 [15:8] reserved bi_unipolar1 re fbuf1+ refbuf1? ainbuf1+ ainbuf1? 0x1320 rw [7:0] burnout_en1 reserved ref_sel1 reserved 0x22 setupcon2 [15:8] reserved bi_unipolar2 re fbuf2+ refbuf2? ainbuf2+ ainbuf2? 0x1320 rw [7:0] burnout_en2 reserved ref_sel2 reserved 0x23 setupcon3 [15:8] reserved bi_unipolar3 re fbuf3+ refbuf3? ainbuf3+ ainbuf3? 0x1320 rw [7:0] burnout_en3 reserved ref_sel3 reserved 0x28 filtcon0 [15:8] sinc3_map0 reserved enhfilten0 enhfilt0 0x0507 rw [7:0] reserved order0 odr0 0x29 filtcon1 [15:8] sinc3_map1 reserved enhfilten1 enhfilt1 0x0507 rw [7:0] reserved order1 odr1 0x2a filtcon2 [15:8] sinc3_map2 re served enhfilten2 enhfilt2 0x0507 rw [7:0] reserved order2 odr2 0x2b filtcon3 [15:8] sinc3_map3 re served enhfilten3 enhfilt3 0x0507 rw [7:0] reserved order3 odr3 0x30 offset0 [23:0] offset0[23:0] 0x800000 rw 0x31 offset1 [23:0] offset1[23:0] 0x800000 rw 0x32 offset2 [23:0] offset2[23:0] 0x800000 rw 0x33 offset3 [23:0] offset3[23:0] 0x800000 rw 0x38 gain0 [23:0] gain0[23:0] 0x5xxxx0 rw 0x39 gain1 [23:0] gain1[23:0] 0x5xxxx0 rw 0x3a gain2 [23:0] gain2[23:0] 0x5xxxx0 rw 0x3b gain3 [23:0] gain3[23:0] 0x5xxxx0 rw
ad7177- 2 data sheet rev. a | page 48 of 59 register details communications regis ter address: 0x00, reset: 0x00, name: comms all access to the on - chip registers must start with a write to the c ommunications r egister . this write determines what register is accessed next and whether that operation is a write or a read. table 25 . bit descriptions for comms bits bit name settings description reset access 7 wen this bit must be low to begin communications with the adc. 0x0 w 6 r/ w this bit determines if the command is a read or write operation. 0x0 w 0 write command 1 read command [5:0] ra the register address bits determine which register is to be read from or written to as part of the current communication. 0x00 w 000000 status r egister 000001 adc m ode r egister 000010 interface m ode r egister 000011 register c hecksum r egister 000100 data r egister 000110 gpio c onfiguration r egister 000111 id r egister 010000 channel 0 r egister 010001 channel 1 r egister 010010 channel 2 r egister 010011 channel 3 r egister 100000 setup configuration 0 r egister 100001 setup configuration 1 r egister 100010 setup configuration 2 r egister 100011 setup configuration 3 r egister 101000 filter configuration 0 r egister 101001 filter configuration 1 r egister 101010 filter configuration 2 r egister 101011 filter configuration 3 r egister 110000 offset 0 r egister 110001 offset 1 r egister 110010 offset 2 r egister 110011 offset 3 r egister 111000 gain 0 r egister 111001 gain 1 r egister 111010 gain 2 r egister 111011 gain 3 r egister
dat a sheet ad7177- 2 rev. a | page 49 of 59 status register address: 0x00, reset: 0x80, name: status the s tatus r egister is an 8 - bit register that contains adc and serial interface status information. it can optionally be appended to the d ata r egister by setting the data_stat bit in the i nterface m ode r egister. table 26 . bit descriptions for sta tus bits bit name settings description reset access 7 rdy the status of rdy is output to the dout/ rdy pin whenever cs is low and a register is not being read. this bit goes low when the adc has written a new result to the data r egister. in adc calibration modes, this bit goes low when the adc has written the calibration result. rdy is brought high a utomatically by a read of the data register . 0x1 r 0 new data result available 1 awaiting new data result 6 adc_error this bit by default indicates if an adc overrange or underrange has occurred. the adc result is clamped to 0xffffff for overrange errors and 0x000000 for underrange errors . this bit is updated when the adc result is writ ten and is cleared at the next update after removing the overrange or underrange condition. 0x0 r 0 no e rror 1 error 5 crc_error this bit indicates if a crc error has taken place during a register write. for register reads, the host microcontroller determines if a crc error has occurred. this bit is cleared by a read of this register. 0x0 r 0 no e rror 1 crc e rror 4 reg_error this bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. the check is activated by setting the reg_check bit in the i nterface m ode r egister. this bit is cleare d by clearing the reg_check bit. 0x0 r 0 no e rror 1 error [3:2] reserved these bits are reserved. 0x0 r [1:0] channel these bits indicate which channel was active for the adc conversion whose result is currently in the d ata r egister. this may be different from the channel currently being converted. the mapping is a direct map from the c hannel r egister; therefore, channel 0 results in 0x0 and channel 3 results in 0x3. 0x0 r 00 channel 0 01 channel 1 10 channel 2 11 channel 3
ad7177- 2 data sheet rev. a | page 50 of 59 adc mode register address: 0x01, reset: 0x8000, name: adcmode the adc m ode r egister controls the operating mode of the adc and the master clock selection. a write to the adc m ode r egister resets the filter and the rdy bits and starts a new conversion or calibration. table 27 . bit descriptions for adcmode bits bit name settings description reset access 15 ref_en enables internal reference and outputs a buffered 2.5 v to the refout pin. 0x1 rw 0 disabled 1 enabled 14 hide_delay if a programmable delay is set using the delay bits , this bit allows the delay to be hidden by absorbing the delay into the conversion time for selected data rates with the s inc5 + s in c 1 filter. see the delay section for more information . 0x0 rw 0 enabled 1 disabled 13 sing_cyc this bit can be used when only a single channel is active to set the adc to only output at the settled filter data rate. 0x0 rw 0 disabled 1 enabled [12:11] reserved these bits are reserved; set these bits to 0. 0x0 r [10:8] delay these bits allow a programmable delay to be added after a channel switch to allow the settling of external circuitry before the adc starts processing its input. 0x0 rw 000 0 s 001 4 s 010 16 s 011 40 s 100 100 s 101 200 s 110 500 s 111 1 ms 7 reserved this bit is reserved; set this bit to 0. 0x0 r [6:4] mode these bits control the operating mode of the adc. see the operating modes section for more information . 0x0 rw 000 continuous c onversion m ode 001 single c onversion m ode 010 standby m ode 011 power - d own m ode 100 internal o ffset c alibration 110 system o ffset c alibration 111 system g ain c alibration [3:2] clocksel the s e bit s are used to select the adc clock source. selecting the internal oscillator also enables the internal oscillator. 0x0 rw 00 internal oscillator 01 internal oscillator output on the xtal2 /clkio pin 10 external clock input on the xtal2 /clkio pin 11 external crystal on the xtal1 and xtal2 /clkio pins [1:0] reserved these bits are reserved; set these bits to 0. 0x0 r
dat a sheet ad7177- 2 rev. a | page 51 of 59 interface mode register address: 0x02, reset: 0x0000, name: ifmode the i nterface m ode r egister configures various serial interface options. table 28 . bit descriptions for ifmode bits bit name settings description reset access [15:13] reserved these bits are reserved; set these bits to 0. 0x0 r 12 a lt_ sync this bit enables a different behavior of the sync / error pin to allow the use of sync / error as a control for conversions when cycling channels (see the description of the sync_en bit in the gpio configuration register section for details). 0x0 rw 0 disabled 1 enabled 11 iostrength this bit controls the drive strength of the dout / rdy pin. set t his bit when reading from the serial interface at high speed with a low iovdd supply and moderate capacitance. 0x0 rw 0 disabled (default) 1 enabled [10: 9 ] reserved these bits are reserved; set these bits to 0. 0x0 r 8 dout_reset see the dout_reset section for more information . 0x0 rw 0 disabled 1 enabled 7 contread this bit enables continuous read mode of the adc data register. the adc must be configured in continuous conversion mode to use continuous read mode . for more details, see the operating modes section. 0x0 rw 0 disabled 1 enabled 6 data_stat this bit enables the s tatus r egister to be appended to the data register when read so that channel and status information are transmitted with the data. this is the only way to be sure that the channel bits read from the status register correspond to the data in the data register . 0x0 rw 0 disabled 1 enabled 5 reg_check this bit enables a register integrity checker, which can be used to monitor any change in the value of the user registers. to use this feature, configure all other registers as desired with this bit cleared. then write to this register to set the reg_check bit to 1. if the contents of any of the registers change, the reg_error bit is set in the status register . to clear the error, set the reg_chec k bit to 0. neither the interface mode register nor the adc d ata or st atus register s are included in the registers that are checked. if a register must have a new value written, this bit must first be cleared; otherwise, an error is flagged when the new register contents are written. 0x0 rw 0 disabled 1 enabled 4 reserved this bit is reserved; set this bit to 0. 0x0 r [3:2] crc_en these bits e nable crc protection of register reads/writes. crc increases the number of bytes in a serial interface transfer by one. see the crc calculation section for more details. 0x00 rw 00 disabled 01 xor checksum enabled for register read transactions; register writes still use crc with these bits set 10 crc checksum enabled for read and write transactions
ad7177- 2 data sheet rev. a | page 52 of 59 bits bit name settings description reset access 1 wl 32 this bit c hanges the adc data register length . the adc is not reset by a write to the interface mode register; therefore, the adc result is not changed to the correct word length immediately after writing to these bits. the first new adc result is correct. 0x0 rw 0 24 - bit data 1 32- bit data 0 reserved this bit is reserved; set this bit to 0. 0x0 r register check address: 0x03, reset: 0x000000, name: regcheck the r egister c heck r egister is a 24 - bit checksum calculated by exclusively or'ing the contents of the user registers. the reg_check bit in the i nterface m ode r egister must be set for this to operate; otherwise, the register reads 0. table 29 . bit descriptions for regcheck bits bit name settings description reset access [23:0] register_check this register contains the 24 - bit checksum of user registers when the reg_check bit is set in the interface mode register . 0x000000 r data register address: 0x04, reset: 0x000000, name: data the d ata r egister contains the adc conversion result. the encoding is offset binary, or it can be changed to unipolar by the bi_unipolar x bit s in the s etup c onfiguration r egister s . reading the d ata r egister brings the rdy bit and the rdy output high if it is low. the adc result can be read multiple times; however, because the rdy output is brought high, it is not possible to know if another adc result is imminent. after the command to read the adc register is received , t he adc does not write a new result into the data register . table 30 . bit descriptions for data bits bit name settings description reset access [ 31 :0] data this register contains the adc conversion result. the size of this register is determined by the wl 32 bits in the interface mode register . 0x000000 r
dat a sheet ad7177- 2 rev. a | page 53 of 59 gpio configuration r egister address: 0x06, reset: 0x0800, name: gpiocon the gpio c onfiguration r egister controls the general - purpose i/o pins of the adc. table 31 . bit descriptions for gpiocon bits bit name settings description reset access [15:13] reserved these bits are reserved; set these bits to 0. 0x0 r 12 mux_io this bit allows the adc to control an external multiplexer, using gpio0/gpio1 in sync with the internal channel sequencing. the analog input pins used for a channel can still be selected on a per channel basis. therefore, it is possible to have a 4 - channel multiplexer in front of ain0/ain1 and another in front of ain2/ain3, giving a total of eight differential channels with the ad71 77 -2 . however, only four channel s at a time can be automatically sequenced. a delay can be inserted after switching an external multiplexer (see the delay bits in the adc mode register section ). 0x0 rw 11 sync_en this bit enables the sync / error pin as a sync input. when the pin is low, this holds the adc and filter in reset until the syn c / error pin goes high. an alternative operation of the sync / error pin is available when the alt_sync bit in the interface mode register is set. this mode only works when multiple chan nels are enabled. in this case, a low on the sync / error pin does not immediately reset the filter/modulator. instead, if the sync / error pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. bringing sync / error high begins the next conversion. this alterna - tive sync mode allows sync / error to be used while cycling through channels. 0x1 rw 0 disabled . 1 enabled . [10:9] err_en these bits enable the sync / error pin as an error input/output. 0x0 rw 00 disabled . 01 sync / error is an error input. the (inverted) readback state is or'ed with other error sources and is available in the adc_error bit in the status register . the sync / error pin state can also be read from the err_dat bit in this register. 10 sync / error is an open - drain error output. the status register error bits are or'ed, inverted, and mapped to the sync / error pin. the sync / error pins of multiple devices can be wired together to a common pull - up resistor so tha t an error on any device can be observed. 11 sync / error is a general - purpose output. the status of the pin is controlled by the err_dat bit in this register. this output is referenced between iovdd and dgnd, as opposed to the avdd1 and avss levels used by the general - purpose i/o pins. the sync / error pin has an active pull - up in this case. 8 err_dat this bit determines the logic level at the sync / error pin if the pin is enabled as a general - purpose output. this bit reflects the readback status of the pin if the pin is enabled as an input. 0x0 rw [7:6] reserved these bits are reserved; set these b its to 0. 0x0 r 5 ip_en1 this bit t urns gpio1 into an input. inputs are referenced to avdd 1 or avss. 0x0 rw 0 disabled . 1 enabled . 4 ip_en0 this bit turns gpio0 into an input. inputs are referenced to avdd1 or avss. 0x0 rw 0 disabled . 1 enabled . 3 op_en1 this bit turns gpio1 into an output. outputs are referenced between avdd1 and avss. 0x0 rw 0 disabled . 1 enabled . 2 op_en0 this bit turns gpio0 into an output. outputs are referenced between avdd1 and avss. 0x0 rw 0 disabled . 1 enabled . 1 gp_data1 this bit is the readback or write data for gpio1. 0x0 rw 0 gp_data0 this bit is the readback or write data for gpio0. 0x0 rw
ad7177- 2 data sheet rev. a | page 54 of 59 id register address: 0x07, reset: 0x4fdx , name: id the id register returns a 16 - bit id. for the ad7177 - 2 , this id is 0x4fdx . table 32 . bit descriptions for id bits bit name settings description reset access [15:0] id the id register returns a 16 - bit id code that is specific to the adc. 0x4fdx r 0x4fdx ad7177 -2 channel register 0 address: 0x10, reset: 0x8001, name: ch 0 the c hannel r egisters are 16 - bit registers used to select which channels are currently active, which inputs are selected for each channel, and which setup is used to configure the adc for that channel. table 33 . bit descriptions for ch 0 bits bit n ame settings description reset access 15 ch_en0 this bit enables channel 0. if more than one channel is enabled, the adc automatically sequence s between them. 0x1 rw 0 disabled 1 enabled (default) 14 reserved this bit is reserved; set this bit to 0. 0x0 r [13:12] setup_sel0 these bits identify which of the four setups is used to configure the adc for this channel. a setup comprises a set of four registers: setup configuration register , filter configuration register , offset register , and g ain r egister. all channels can use the same setup, in which case the same 2 - bit value must be written to these bits on all active channels, or up to four channels can be configured differently. 0x0 rw 00 setup 0 01 setup 1 10 setup 2 11 setup 3 [11:10] reserved these bits are reserved; set these bits to 0. 0x0 r [9:5] ainpos0 these bits select which input is connected to the positive input of the adc for this channel. 0x0 rw 00000 ain0 (default) 00001 ain1 00010 ain2 00011 ain3 00100 ain4 10001 t emperature sensor + 10010 temperature sensor ? 10011 ((avdd1 ? avss)/ 5) + ( a nalog i nput b uffers must be enabled) 10100 ((avdd1 ? avss ) /5) ? ( a nalog i nput buffers must be enabled ) 10101 ref+ 10110 ref?
data sheet AD7177-2 rev. a | page 55 of 59 bits bit name settings description reset access [4:0] ainneg0 these bits select which input is conne cted to the negative input of the adc for this channel. 0x1 rw 00000 ain0 00001 ain1 (default) 00010 ain2 00011 ain3 00100 ain4 10001 temperature sensor+ 10010 temperature sensor? 10011 ((avdd1 ? avss)/5)+ 10100 ((avdd1 ? avss)/5)? 10101 ref+ 10110 ref? channel register 1 to channel register 3 address: 0x11 to 0x13, reset: 0x0001, name: ch1 to ch3 the remaining three channel registers share the same layout as channel register 0. table 34. ch1 to ch3 register map reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x11 ch1 [15:8] ch_en1 reserved setup_sel1 reserved ainpos1[4:3] 0x0001 rw [7:0] ainpos1[2:0] ainneg1 0x12 ch2 [15:8] ch_en2 reserved setup_sel2 reserved ainpos2[4:3] 0x0001 rw [7:0] ainpos2[2:0] ainneg2 0x13 ch3 [15:8] ch_en3 reserved setup_sel3 reserved ainpos3[4:3] 0x0001 rw [7:0] ainpos3[2:0] ainneg3
AD7177-2 data sheet rev. a | page 56 of 59 setup configuration register 0 address: 0x20, reset: 0x1320, name: setupcon0 the setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the adc. table 35. bit descriptions for setupcon0 bits bit name settings description reset access [15:13] reserved these bits are re served; set these bits to 0. 0x0 r 12 bi_unipolar0 this bit sets the output coding of the adc for setup 0. 0x1 rw 0 unipolar coded output 1 bipolar coded output (offset binary) 11 refbuf0+ this bit enables or disa bles the ref+ input buffer. 0x0 rw 0 ref+ buffer disabled 1 ref+ buffer enabled 10 refbuf0? this bit enables or disa bles the ref? input buffer. 0x0 rw 0 ref? buffer disabled 1 ref? buffer enabled 9 ainbuf0+ this bit enables or disa bles the ain+ input buffer. 0x1 rw 0 ain+ buffer disabled 1 ain+ buffer enabled 8 ainbuf0? this bit enables or disa bles the ain? input buffer. 0x1 rw 0 ain? buffer disabled 1 ain? buffer enabled 7 burnout_en0 this bit enables a 10 a current sour ce on the positive analog input selected and a 10 a current sink on the negative analog input selected. the burnout currents are useful in diagnosis of an open wire, whereby the adc result goes to full scale. enab ling the burnout currents during measurement results in an offset voltage on the adc. this means the strategy for diagnosing an open wire operates best by turning on the burnout currents at intervals, before or after precision measurements. 0x00 r 6 reserved these bits are reserv ed; set these bits to 0. 0x00 r [5:4] ref_sel0 these bits allow the user to select the reference source for adc conversion on setup 0. 0x2 rw 00 external reference. 10 internal 2.5 v reference. this must also be enabled in the adc mode register. 11 avdd1 ? avss. this can be used to as a diagnostic to validate other reference values. [3:0] reserved these bits are rese rved; set these bits to 0. 0x0 r setup configuration register 1 to setup configuration register 3 address: 0x21 to 0x23, reset: 0x1320, name: setupcon1 to setupcon3 the remaining three setup configuration registers share the same layout as setup configuration register 0. table 36. setupcon1 to setupcon3 register map reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x21 setupcon1 [15:8] reserved bi_unipolar1 re fbuf1+ refbuf1? ainbuf1+ ainbuf1? 0x1320 rw [7:0] burnout_en1 reserved ref_sel1 reserved 0x22 setupcon2 [15:8] reserved bi_unipolar2 re fbuf2+ refbuf2? ainbuf2+ ainbuf2? 0x1320 rw [7:0] burnout_en2 reserved ref_sel2 reserved 0x23 setupcon3 [15:8] reserved bi_unipolar3 re fbuf3+ refbuf3? ainbuf3+ ainbuf3? 0x1320 rw [7:0] burnout_en3 reserved ref_sel3 reserved
dat a sheet ad7177- 2 rev. a | page 57 of 59 filter configuration register 0 address: 0x28, reset: 0x0507 , name: filtcon0 the f ilter c onfiguration r egisters are 16 - bit registers that configure the adc data rate and filter options. writing to any of these registers resets any active adc conversion and restarts converting at the first channel in the sequence. table 37 . bit descriptions for filtcon0 bits bit name settings description reset access 15 sinc3_map0 if this bit is set, the mapping of the f ilter r egister changes to directly program the decimation rate of the sinc3 filter for setup 0. all other options are eliminated. this allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. the data rate when on a sing le channel equals f mod /(32 filtcon0[14:0]). 0x0 rw [14:12] reserved these bits are reserved; set these bits to 0. 0x0 r 11 enhfilten0 this bit enables various post filters for enhanced 50 hz/60 hz rejection for setup 0. the order 0 bits must be set to 00 to select the sinc5 + sinc1 filter for this to work. 0x0 rw 0 disabled 1 enabled [10:8] enhfilt0 these bits select between various postfilters for enhanced 50 hz/60 hz rejection for setup 0. 0x5 rw 010 27 sps, 47 db rejection, 36.7 ms settling 011 25 sps, 62 db rejection, 40 ms settling 101 20 sps, 8 5 db rejection, 50 ms settling 110 16.67 sps, 92 db rejection, 60 ms settling 7 reserved this bit is reserved; set this bit to 0. 0x0 r [6:5] order0 these bits control the order of the digital filter that processes the modulator data for setup 0. 0x0 rw 00 sinc5 + s inc1 (default) 11 sinc3 [4:0] odr0 these bits control the output data rate of the adc and, therefore, the settling time and noise for setup 0. rates shown a re for the s inc5 + sinc 1 filter. see table 19 to table 22. 0x0 7 rw 00000 to 00110 reserved 00111 10,000 sps 01000 5000 sps 01001 2500 sps 01010 1000 sps 01011 500 sps 01100 397.5 sps 01101 200 sps 01110 100 sps 01111 59.92 sps 10000 49.96 sps 10001 20 sps 10010 16.66 sps 10011 10 sps 10100 5 sps
AD7177-2 data sheet rev. a | page 58 of 59 filter configuration register 1 to filter configuration register 3 address: 0x29 to 0x2b, reset: 0x0507, name: filtcon1 to filtcon3 the remaining three filter configuration registers share the same layout as filter configuration register 0. table 38. filtcon1 to filtcon3 register map reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x29 filtcon1 [15:8] sinc3_map1 reserved enhfilten1 enhfilt1 0x0507 rw [7:0] reserved order1 odr1 0x2a filtcon2 [15:8] sinc3_map2 reserved enhfilten2 enhfilt2 0x0507 rw [7:0] reserved order2 odr2 0x2b filtcon3 [15:8] sinc3_map3 reserved enhfilten3 enhfilt3 0x0507 rw [7:0] reserved order3 odr3 offset register 0 address: 0x30, reset: 0x800000, name: offset0 the offset (zero-scale) registers are 24-bit registers that can be used to compensate for any offset error in the adc or in the system. table 39. bit descriptions for offset0 bits bit name settings description reset access [23:0] offset0 offset calibration coefficient for setup 0. 0x800000 rw offset register 1 to offset register 3 address: 0x31 to 0x33, reset: 0x800000, name: offset1 to offset3 the remaining three offset registers share the same layout as offset register 0. table 40. offset1 to offset3 register map reg. name bits reset rw 0x31 offset1 offset1[23:0] 0x800000 rw 0x32 offset2 offset2[23:0] 0x800000 rw 0x33 offset3 offset3[23:0] 0x800000 rw gain register 0 address: 0x38, reset: 0x5xxxx0, name: gain0 the gain (full-scale) registers are 24-bit registers that can be used to compensate for any gain error in the adc or in the sys tem. table 41. bit descriptions for gain0 bits bit name settings description reset access [23:0] gain0 gain calibration coe fficient for setup 0. 0x5xxxx0 rw gain register 1 to gain register 3 address: 0x39 to 0x3b, reset: 0x5xxxx0, name: gain1 to gain3 the remaining three gain registers share the same layout as gain register 0. table 42. gain1 to gain3 register map reg. name bits reset rw 0x39 gain1 gain1[23:0] 0x5xxxx0 rw 0x3a gain2 gain2[23:0] 0x5xxxx0 rw 0x3b gain3 gain3[23:0] 0x5xxxx0 rw
dat a sheet ad7177- 2 rev. a | page 59 of 59 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 71 . 24 - lead thin shrink small outline package [tssop] (ru - 24) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad7177 -2 bruz ? 40c to +105c 24- lead thin shrink small outline package [tssop] ru -24 ad7177 -2 bruz - rl7 ? 40c to +105c 24- lead thin shrink small outline package [tssop] ru -24 1 z = rohs compliant part. ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12912 - 0 - 9/15(a)

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